+ User Manual
http://dl.linux-sunxi.org/A33/A33%20user%20manual%20release%201.1.pdf
+ - Allwinner H2+ (sun8i)
+ + No document available now, but is known to be working properly with
+ H3 drivers and memory map.
+
- Allwinner H3 (sun8i)
+ Datasheet
http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf
+ - Allwinner V3s (sun8i)
+ + Datasheet
+ http://linux-sunxi.org/File:Allwinner_V3s_Datasheet_V1.0.pdf
+
* Quad ARM Cortex-A15, Quad ARM Cortex-A7 based SoCs
- Allwinner A80
+ Datasheet
"marvell,armada-380-smp"
"marvell,armada-390-smp"
"marvell,armada-xp-smp"
+ "marvell,98dx3236-smp"
"mediatek,mt6589-smp"
"mediatek,mt81xx-tz-smp"
"qcom,gcc-msm8660"
--- /dev/null
+Resume Control
+--------------
+Available on Marvell SOCs: 98DX3336 and 98DX4251
+
+Required properties:
+
+- compatible: must be "marvell,98dx3336-resume-ctrl"
+
+- reg: Should contain resume control registers location and length
+
+Example:
+
+resume@20980 {
+ compatible = "marvell,98dx3336-resume-ctrl";
+ reg = <0x20980 0x10>;
+};
allwinner,sun8i-a23
allwinner,sun8i-a33
allwinner,sun8i-a83t
+ allwinner,sun8i-h2-plus
allwinner,sun8i-h3
allwinner,sun9i-a80
allwinner,sun50i-a64
- i80-if-timings: timing configuration for lcd i80 interface support.
Optional Properties:
-- samsung,power-domain: a phandle to DECON power domain node.
+- power-domains: a phandle to DECON power domain node.
- display-timings: timing settings for DECON, as described in document [1].
Can be used in case timings cannot be provided otherwise
or to override timings provided by the panel.
N: efm32
ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6)
-M: Daniel Ribeiro <drwyrm@gmail.com>
-M: Stefan Schmidt <stefan@openezx.org>
-M: Harald Welte <laforge@openezx.org>
-L: openezx-devel@lists.openezx.org (moderated for non-subscribers)
-W: http://www.openezx.org/
+M: Robert Jarzmik <robert.jarzmik@free.fr>
+L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
-T: topgit git://git.openezx.org/openezx.git
F: arch/arm/mach-pxa/ezx.c
ARM/FARADAY FA526 PORT
M: Eric Anholt <eric@anholt.net>
L: linux-rpi-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/rpi/linux-rpi.git
+T: git git://github.com/anholt/linux
S: Maintained
N: bcm2835
F: drivers/staging/vc04_services
S: Supported
F: tools/objtool/
-OMAP SUPPORT
+OMAP1 SUPPORT
+M: Aaro Koskinen <aaro.koskinen@iki.fi>
+M: Tony Lindgren <tony@atomide.com>
+L: linux-omap@vger.kernel.org
+Q: http://patchwork.kernel.org/project/linux-omap/list/
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
+S: Maintained
+F: arch/arm/mach-omap1/
+F: arch/arm/plat-omap/
+F: arch/arm/configs/omap1_defconfig
+F: drivers/i2c/busses/i2c-omap.c
+F: include/linux/i2c-omap.h
+
+OMAP2+ SUPPORT
M: Tony Lindgren <tony@atomide.com>
L: linux-omap@vger.kernel.org
W: http://www.muru.com/linux/omap/
Q: http://patchwork.kernel.org/project/linux-omap/list/
T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git
S: Maintained
-F: arch/arm/*omap*/
-F: arch/arm/configs/omap1_defconfig
+F: arch/arm/mach-omap2/
+F: arch/arm/plat-omap/
F: arch/arm/configs/omap2plus_defconfig
F: drivers/i2c/busses/i2c-omap.c
F: drivers/irqchip/irq-omap-intc.c
select WATCHDOG
select ASPEED_WATCHDOG
select MOXART_TIMER
+ select MFD_SYSCON
+ select PINCTRL
help
Say Y here if you want to run your kernel on an ASpeed BMC SoC.
bool "Aspeed SoC 4th Generation"
depends on ARCH_MULTI_V5
select CPU_ARM926T
+ select PINCTRL_ASPEED_G4
help
Say yes if you intend to run on an Aspeed ast2400 or similar
fourth generation BMCs, such as those used by OpenPower Power8
bool "Aspeed SoC 5th Generation"
depends on ARCH_MULTI_V6
select CPU_V6
+ select PINCTRL_ASPEED_G5
help
Say yes if you intend to run on an Aspeed ast2500 or similar
fifth generation Aspeed BMCs.
int memctrl;
} at91_pm_data;
-void __iomem *at91_ramc_base[2];
+static void __iomem *at91_ramc_base[2];
static int at91_pm_valid_state(suspend_state_t state)
{
#include <soc/at91/at91sam9_sdramc.h>
#ifndef __ASSEMBLY__
-extern void __iomem *at91_ramc_base[];
-
#define at91_ramc_read(id, field) \
__raw_readl(at91_ramc_base[id] + field)
obj-$(CONFIG_CP_INTC) += cp_intc.o
# Board specific
-obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o
+obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o pdata-quirks.o
obj-$(CONFIG_MACH_DAVINCI_EVM) += board-dm644x-evm.o
obj-$(CONFIG_MACH_SFFSDR) += board-sffsdr.o
obj-$(CONFIG_MACH_NEUROS_OSD2) += board-neuros-osd2.o
CLK("spi_davinci.0", NULL, &spi0_clk),
CLK("spi_davinci.1", NULL, &spi1_clk),
CLK("vpif", NULL, &vpif_clk),
- CLK("ahci_da850", NULL, &sata_clk),
+ CLK("ahci_da850", "fck", &sata_clk),
CLK("davinci-rproc.0", NULL, &dsp_clk),
CLK(NULL, NULL, &ehrpwm_clk),
CLK("ehrpwm.0", "fck", &ehrpwm0_clk),
OF_DEV_AUXDATA("ti,da830-ohci", 0x01e25000, "ohci-da8xx", NULL),
OF_DEV_AUXDATA("ti,da830-musb", 0x01e00000, "musb-da8xx", NULL),
OF_DEV_AUXDATA("ti,da830-usb-phy", 0x01c1417c, "da8xx-usb-phy", NULL),
+ OF_DEV_AUXDATA("ti,da850-ahci", 0x01e18000, "ahci_da850", NULL),
{}
};
static void __init da850_init_machine(void)
{
+ /* All existing boards use 100MHz SATA refclkpn */
+ static const unsigned long sata_refclkpn = 100 * 1000 * 1000;
+
int ret;
ret = da8xx_register_usb20_phy_clk(false);
pr_warn("%s: registering USB 1.1 PHY clock failed: %d",
__func__, ret);
+ ret = da850_register_sata_refclk(sata_refclkpn);
+ if (ret)
+ pr_warn("%s: registering SATA REFCLK failed: %d",
+ __func__, ret);
+
of_platform_default_populate(NULL, da850_auxdata_lookup, NULL);
davinci_pm_init();
+ pdata_quirks_init();
}
static const char *const da850_boards_compat[] __initconst = {
#include <mach/common.h>
#include <mach/time.h>
#include <mach/da8xx.h>
+#include <mach/clock.h>
#include "cpuidle.h"
#include "sram.h"
}
#ifdef CONFIG_ARCH_DAVINCI_DA850
+static struct clk sata_refclk = {
+ .name = "sata_refclk",
+ .set_rate = davinci_simple_set_rate,
+};
+
+static struct clk_lookup sata_refclk_lookup =
+ CLK("ahci_da850", "refclk", &sata_refclk);
+
+int __init da850_register_sata_refclk(int rate)
+{
+ int ret;
+
+ sata_refclk.rate = rate;
+ ret = clk_register(&sata_refclk);
+ if (ret)
+ return ret;
+
+ clkdev_add(&sata_refclk_lookup);
+
+ return 0;
+}
+
static struct resource da850_sata_resources[] = {
{
.start = DA850_SATA_BASE,
int __init da850_register_sata(unsigned long refclkpn)
{
- /* please see comment in drivers/ata/ahci_da850.c */
- BUG_ON(refclkpn != 100 * 1000 * 1000);
+ int ret;
+
+ ret = da850_register_sata_refclk(refclkpn);
+ if (ret)
+ return ret;
return platform_device_register(&da850_sata_device);
}
static inline int davinci_pm_init(void) { return 0; }
#endif
+void __init pdata_quirks_init(void);
+
#define SRAM_SIZE SZ_128K
#endif /* __ARCH_ARM_MACH_DAVINCI_COMMON_H */
int da8xx_register_usb_refclkin(int rate);
int da8xx_register_usb20_phy_clk(bool use_usb_refclkin);
int da8xx_register_usb11_phy_clk(bool use_usb_refclkin);
+int da850_register_sata_refclk(int rate);
int da8xx_register_emac(void);
int da8xx_register_uio_pruss(void);
int da8xx_register_lcdc(struct da8xx_lcdc_platform_data *pdata);
--- /dev/null
+/*
+ * Legacy platform_data quirks
+ *
+ * Copyright (C) 2016 BayLibre, Inc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/of_platform.h>
+
+#include <mach/common.h>
+
+struct pdata_init {
+ const char *compatible;
+ void (*fn)(void);
+};
+
+static void pdata_quirks_check(struct pdata_init *quirks)
+{
+ while (quirks->compatible) {
+ if (of_machine_is_compatible(quirks->compatible)) {
+ if (quirks->fn)
+ quirks->fn();
+ break;
+ }
+ quirks++;
+ }
+}
+
+static struct pdata_init pdata_quirks[] __initdata = {
+ { /* sentinel */ },
+};
+
+void __init pdata_quirks_init(void)
+{
+ pdata_quirks_check(pdata_quirks);
+}
*/
#include <mach/ep93xx-regs.h>
+#include <asm/mach-types.h>
static unsigned char __raw_readb(unsigned int ptr)
{
;
}
+#define TS72XX_WDT_CONTROL_PHYS_BASE 0x23800000
+#define TS72XX_WDT_FEED_PHYS_BASE 0x23c00000
+#define TS72XX_WDT_FEED_VAL 0x05
+
+static void __maybe_unused ts72xx_watchdog_disable(void)
+{
+ __raw_writeb(TS72XX_WDT_FEED_VAL, TS72XX_WDT_FEED_PHYS_BASE);
+ __raw_writeb(0, TS72XX_WDT_CONTROL_PHYS_BASE);
+}
static void arch_decomp_setup(void)
{
+ if (machine_is_ts72xx())
+ ts72xx_watchdog_disable();
ethernet_reset();
}
default y
depends on ARCH_EXYNOS4
-config SOC_EXYNOS4415
- bool "SAMSUNG EXYNOS4415"
- default y
- depends on ARCH_EXYNOS4
-
config SOC_EXYNOS5250
bool "SAMSUNG EXYNOS5250"
default y
.id = -1,
};
-void __iomem *sysram_base_addr;
-void __iomem *sysram_ns_base_addr;
+void __iomem *sysram_base_addr __ro_after_init;
+void __iomem *sysram_ns_base_addr __ro_after_init;
void __init exynos_sysram_init(void)
{
"samsung,exynos4210",
"samsung,exynos4212",
"samsung,exynos4412",
- "samsung,exynos4415",
"samsung,exynos5",
"samsung,exynos5250",
"samsung,exynos5260",
#define EXYNOS5420_USE_ARM_CORE_DOWN_STATE BIT(29)
#define EXYNOS5420_USE_L2_COMMON_UP_STATE BIT(30)
-static void __iomem *ns_sram_base_addr;
+static void __iomem *ns_sram_base_addr __ro_after_init;
/*
* The common v7_exit_coherency_flush API could not be used because of the
int (*cpu_suspend)(unsigned long);
};
-static const struct exynos_pm_data *pm_data;
+static const struct exynos_pm_data *pm_data __ro_after_init;
static int exynos5420_cpu_state;
static unsigned int exynos_pmu_spare3;
EXYNOS_PMU_IRQ(exynos4210_pmu_irq, "samsung,exynos4210-pmu");
EXYNOS_PMU_IRQ(exynos4212_pmu_irq, "samsung,exynos4212-pmu");
EXYNOS_PMU_IRQ(exynos4412_pmu_irq, "samsung,exynos4412-pmu");
-EXYNOS_PMU_IRQ(exynos4415_pmu_irq, "samsung,exynos4415-pmu");
EXYNOS_PMU_IRQ(exynos5250_pmu_irq, "samsung,exynos5250-pmu");
EXYNOS_PMU_IRQ(exynos5420_pmu_irq, "samsung,exynos5420-pmu");
extern void hix5hd2_cpu_die(unsigned int cpu);
extern void hip01_set_cpu(int cpu, bool enable);
-extern void hip01_cpu_die(unsigned int cpu);
#endif
#define imx_flexcan_data_entry(soc, _id, _hwid, _size) \
[_id] = imx_flexcan_data_entry_single(soc, _id, _hwid, _size)
-#ifdef CONFIG_SOC_IMX25
-const struct imx_flexcan_data imx25_flexcan_data[] __initconst = {
-#define imx25_flexcan_data_entry(_id, _hwid) \
- imx_flexcan_data_entry(MX25, _id, _hwid, SZ_16K)
- imx25_flexcan_data_entry(0, 1),
- imx25_flexcan_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
#ifdef CONFIG_SOC_IMX35
const struct imx_flexcan_data imx35_flexcan_data[] __initconst = {
#define imx35_flexcan_data_entry(_id, _hwid) \
#define imx_sdhci_esdhc_imx_data_entry(soc, devid, id, hwid) \
[id] = imx_sdhci_esdhc_imx_data_entry_single(soc, devid, id, hwid)
-#ifdef CONFIG_SOC_IMX25
-const struct imx_sdhci_esdhc_imx_data
-imx25_sdhci_esdhc_imx_data[] __initconst = {
-#define imx25_sdhci_esdhc_imx_data_entry(_id, _hwid) \
- imx_sdhci_esdhc_imx_data_entry(MX25, "sdhci-esdhc-imx25", _id, _hwid)
- imx25_sdhci_esdhc_imx_data_entry(0, 1),
- imx25_sdhci_esdhc_imx_data_entry(1, 2),
-};
-#endif /* ifdef CONFIG_SOC_IMX25 */
-
#ifdef CONFIG_SOC_IMX35
const struct imx_sdhci_esdhc_imx_data
imx35_sdhci_esdhc_imx_data[] __initconst = {
#include <linux/regulator/machine.h>
#include <linux/spi/l4f00242t03.h>
-#include <media/soc_camera.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#define SD1_CD IMX_GPIO_NR(2, 26)
#define LCD_RESET IMX_GPIO_NR(1, 3)
#define LCD_ENABLE IMX_GPIO_NR(1, 31)
-#define CSI_PWRDWN IMX_GPIO_NR(4, 19)
-#define CSI_RESET IMX_GPIO_NR(3, 6)
static const int mx27pdk_pins[] __initconst = {
/* UART1 */
PA30_PF_CONTRAST,
LCD_ENABLE | GPIO_GPIO | GPIO_OUT,
LCD_RESET | GPIO_GPIO | GPIO_OUT,
- /* CSI */
- PB10_PF_CSI_D0,
- PB11_PF_CSI_D1,
- PB12_PF_CSI_D2,
- PB13_PF_CSI_D3,
- PB14_PF_CSI_D4,
- PB15_PF_CSI_MCLK,
- PB16_PF_CSI_PIXCLK,
- PB17_PF_CSI_D5,
- PB18_PF_CSI_D6,
- PB19_PF_CSI_D7,
- PB20_PF_CSI_VSYNC,
- PB21_PF_CSI_HSYNC,
- CSI_PWRDWN | GPIO_GPIO | GPIO_OUT,
- CSI_RESET | GPIO_GPIO | GPIO_OUT,
/* SSI4 */
PC16_PF_SSI4_FS,
PC17_PF_SSI4_RXD,
PC19_PF_SSI4_CLK,
};
-static struct gpio mx27_3ds_camera_gpios[] = {
- { CSI_PWRDWN, GPIOF_OUT_INIT_HIGH, "camera-power" },
- { CSI_RESET, GPIOF_OUT_INIT_HIGH, "camera-reset" },
-};
-
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
static struct regulator_consumer_supply vmmc1_consumers[] = {
REGULATOR_SUPPLY("vcore", "spi0.0"),
- REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
};
static struct regulator_init_data vmmc1_init = {
.consumer_supplies = vgen_consumers,
};
-static struct regulator_consumer_supply vvib_consumers[] = {
- REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
-};
-
-static struct regulator_init_data vvib_init = {
- .constraints = {
- .min_uV = 1300000,
- .max_uV = 1300000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
- .consumer_supplies = vvib_consumers,
-};
-
static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
{
.id = MC13783_REG_VMMC1,
}, {
.id = MC13783_REG_GPO3, /* Turn on 3.3V */
.init_data = &gpo_init,
- }, {
- .id = MC13783_REG_VVIB, /* Power OV2640 */
- .init_data = &vvib_init,
},
};
.num_chipselect = ARRAY_SIZE(spi2_chipselect),
};
-static int mx27_3ds_camera_power(struct device *dev, int on)
-{
- /* enable or disable the camera */
- pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
- gpio_set_value(CSI_PWRDWN, on ? 0 : 1);
-
- if (!on)
- goto out;
-
- /* If enabled, give a reset impulse */
- gpio_set_value(CSI_RESET, 0);
- msleep(20);
- gpio_set_value(CSI_RESET, 1);
- msleep(100);
-
-out:
- return 0;
-}
-
-static struct i2c_board_info mx27_3ds_i2c_camera = {
- I2C_BOARD_INFO("ov2640", 0x30),
-};
-
-static struct regulator_bulk_data mx27_3ds_camera_regs[] = {
- { .supply = "cmos_vcore" },
- { .supply = "cmos_2v8" },
-};
-
-static struct soc_camera_link iclink_ov2640 = {
- .bus_id = 0,
- .board_info = &mx27_3ds_i2c_camera,
- .i2c_adapter_id = 0,
- .power = mx27_3ds_camera_power,
- .regulators = mx27_3ds_camera_regs,
- .num_regulators = ARRAY_SIZE(mx27_3ds_camera_regs),
-};
-
-static struct platform_device mx27_3ds_ov2640 = {
- .name = "soc-camera-pdrv",
- .id = 0,
- .dev = {
- .platform_data = &iclink_ov2640,
- },
-};
-
static struct imx_fb_videomode mx27_3ds_modes[] = {
{ /* 480x640 @ 60 Hz */
.mode = {
},
};
-static struct platform_device *devices[] __initdata = {
- &mx27_3ds_ov2640,
-};
-
-static const struct mx2_camera_platform_data mx27_3ds_cam_pdata __initconst = {
- .clk = 26000000,
-};
-
static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = {
.bitrate = 100000,
};
imx27_add_spi_imx0(&spi1_pdata);
imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
- platform_add_devices(devices, ARRAY_SIZE(devices));
imx27_add_imx_fb(&mx27_3ds_fb_data);
imx27_add_imx_ssi(0, &mx27_3ds_ssi_pdata);
static void __init mx27pdk_late_init(void)
{
- int ret;
-
mx27_3ds_sdhc1_enable_level_translator();
imx27_add_mxc_mmc(0, &sdhc1_pdata);
if (mxc_expio_init(MX27_CS5_BASE_ADDR, IMX_GPIO_NR(3, 28)))
pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
- ret = gpio_request_array(mx27_3ds_camera_gpios,
- ARRAY_SIZE(mx27_3ds_camera_gpios));
- if (ret) {
- pr_err("Failed to request camera gpios");
- iclink_ov2640.power = NULL;
- }
-
- imx27_add_mx2_camera(&mx27_3ds_cam_pdata);
imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
}
#include <linux/regulator/machine.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
-#include <linux/memblock.h>
-
-#include <media/soc_camera.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/memory.h>
#include <asm/mach/map.h>
-#include <asm/memblock.h>
#include "3ds_debugboard.h"
#include "common.h"
MX31_PIN_HSYNC__HSYNC,
MX31_PIN_FPSHIFT__FPSHIFT,
MX31_PIN_CONTRAST__CONTRAST,
- /* CSI */
- MX31_PIN_CSI_D6__CSI_D6,
- MX31_PIN_CSI_D7__CSI_D7,
- MX31_PIN_CSI_D8__CSI_D8,
- MX31_PIN_CSI_D9__CSI_D9,
- MX31_PIN_CSI_D10__CSI_D10,
- MX31_PIN_CSI_D11__CSI_D11,
- MX31_PIN_CSI_D12__CSI_D12,
- MX31_PIN_CSI_D13__CSI_D13,
- MX31_PIN_CSI_D14__CSI_D14,
- MX31_PIN_CSI_D15__CSI_D15,
- MX31_PIN_CSI_HSYNC__CSI_HSYNC,
- MX31_PIN_CSI_MCLK__CSI_MCLK,
- MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
- MX31_PIN_CSI_VSYNC__CSI_VSYNC,
- MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
- IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
/* SSI */
MX31_PIN_STXD4__STXD4,
MX31_PIN_SRXD4__SRXD4,
MX31_PIN_SFS4__SFS4,
};
-/*
- * Camera support
- */
-static phys_addr_t mx3_camera_base __initdata;
-#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M
-
-#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
-#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1)
-
-static struct gpio mx31_3ds_camera_gpios[] = {
- { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" },
- { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
-};
-
-static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = {
- .flags = MX3_CAMERA_DATAWIDTH_10,
- .mclk_10khz = 2600,
-};
-
-static int __init mx31_3ds_init_camera(void)
-{
- int dma, ret = -ENOMEM;
- struct platform_device *pdev =
- imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata);
-
- if (IS_ERR(pdev))
- return PTR_ERR(pdev);
-
- if (!mx3_camera_base)
- goto err;
-
- dma = dma_declare_coherent_memory(&pdev->dev,
- mx3_camera_base, mx3_camera_base,
- MX31_3DS_CAMERA_BUF_SIZE,
- DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
-
- if (!(dma & DMA_MEMORY_MAP))
- goto err;
-
- ret = platform_device_add(pdev);
- if (ret)
-err:
- platform_device_put(pdev);
-
- return ret;
-}
-
-static int mx31_3ds_camera_power(struct device *dev, int on)
-{
- /* enable or disable the camera */
- pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
- gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1);
-
- if (!on)
- goto out;
-
- /* If enabled, give a reset impulse */
- gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0);
- msleep(20);
- gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1);
- msleep(100);
-
-out:
- return 0;
-}
-
-static struct i2c_board_info mx31_3ds_i2c_camera = {
- I2C_BOARD_INFO("ov2640", 0x30),
-};
-
-static struct regulator_bulk_data mx31_3ds_camera_regs[] = {
- { .supply = "cmos_vcore" },
- { .supply = "cmos_2v8" },
-};
-
-static struct soc_camera_link iclink_ov2640 = {
- .bus_id = 0,
- .board_info = &mx31_3ds_i2c_camera,
- .i2c_adapter_id = 0,
- .power = mx31_3ds_camera_power,
- .regulators = mx31_3ds_camera_regs,
- .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs),
-};
-
-static struct platform_device mx31_3ds_ov2640 = {
- .name = "soc-camera-pdrv",
- .id = 0,
- .dev = {
- .platform_data = &iclink_ov2640,
- },
-};
-
/*
* FB support
*/
static struct regulator_consumer_supply vmmc1_consumers[] = {
REGULATOR_SUPPLY("vcore", "spi0.0"),
- REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
};
static struct regulator_init_data vmmc1_init = {
.consumer_supplies = vgen_consumers,
};
-static struct regulator_consumer_supply vvib_consumers[] = {
- REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
-};
-
-static struct regulator_init_data vvib_init = {
- .constraints = {
- .min_uV = 1300000,
- .max_uV = 1300000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
- .consumer_supplies = vvib_consumers,
-};
-
static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
{
.id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
}, {
.id = MC13783_REG_VGEN, /* Power LCD */
.init_data = &vgen_init,
- }, {
- .id = MC13783_REG_VVIB, /* Power CMOS */
- .init_data = &vvib_init,
},
};
.bitrate = 100000,
};
-static struct platform_device *devices[] __initdata = {
- &mx31_3ds_ov2640,
-};
-
static void __init mx31_3ds_init(void)
{
imx31_soc_init();
static void __init mx31_3ds_late(void)
{
- int ret;
-
mx31_3ds_spi_devs[0].irq = gpio_to_irq(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
spi_register_board_info(mx31_3ds_spi_devs,
ARRAY_SIZE(mx31_3ds_spi_devs));
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
mx31_3ds_usbotg_init();
if (otg_mode_host) {
otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
"devices on the debug board are unusable.\n");
imx31_add_mxc_mmc(0, &sdhc1_pdata);
-
- /* CSI */
- /* Camera power: default - off */
- ret = gpio_request_array(mx31_3ds_camera_gpios,
- ARRAY_SIZE(mx31_3ds_camera_gpios));
- if (ret) {
- pr_err("Failed to request camera gpios");
- iclink_ov2640.power = NULL;
- }
-
- mx31_3ds_init_camera();
}
static void __init mx31_3ds_timer_init(void)
mx31_clocks_init(26000000);
}
-static void __init mx31_3ds_reserve(void)
-{
- /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
- mx3_camera_base = arm_memblock_steal(MX31_3DS_CAMERA_BUF_SIZE,
- MX31_3DS_CAMERA_BUF_SIZE);
-}
-
MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
/* Maintainer: Freescale Semiconductor, Inc. */
.atag_offset = 0x100,
.init_time = mx31_3ds_timer_init,
.init_machine = mx31_3ds_init,
.init_late = mx31_3ds_late,
- .reserve = mx31_3ds_reserve,
.restart = mxc_restart,
MACHINE_END
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
-#include <asm/memblock.h>
#include <video/platform_lcd.h>
-#include <media/soc_camera.h>
-
#include "3ds_debugboard.h"
#include "common.h"
#include "devices-imx35.h"
MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
- /* CSI */
- MX35_PAD_TX1__IPU_CSI_D_6,
- MX35_PAD_TX0__IPU_CSI_D_7,
- MX35_PAD_CSI_D8__IPU_CSI_D_8,
- MX35_PAD_CSI_D9__IPU_CSI_D_9,
- MX35_PAD_CSI_D10__IPU_CSI_D_10,
- MX35_PAD_CSI_D11__IPU_CSI_D_11,
- MX35_PAD_CSI_D12__IPU_CSI_D_12,
- MX35_PAD_CSI_D13__IPU_CSI_D_13,
- MX35_PAD_CSI_D14__IPU_CSI_D_14,
- MX35_PAD_CSI_D15__IPU_CSI_D_15,
- MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC,
- MX35_PAD_CSI_MCLK__IPU_CSI_MCLK,
- MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK,
- MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC,
/*PMIC IRQ*/
MX35_PAD_GPIO2_0__GPIO2_0,
};
-/*
- * Camera support
-*/
-static phys_addr_t mx3_camera_base __initdata;
-#define MX35_3DS_CAMERA_BUF_SIZE SZ_8M
-
-static const struct mx3_camera_pdata mx35_3ds_camera_pdata __initconst = {
- .flags = MX3_CAMERA_DATAWIDTH_8,
- .mclk_10khz = 2000,
-};
-
-static int __init imx35_3ds_init_camera(void)
-{
- int dma, ret = -ENOMEM;
- struct platform_device *pdev =
- imx35_alloc_mx3_camera(&mx35_3ds_camera_pdata);
-
- if (IS_ERR(pdev))
- return PTR_ERR(pdev);
-
- if (!mx3_camera_base)
- goto err;
-
- dma = dma_declare_coherent_memory(&pdev->dev,
- mx3_camera_base, mx3_camera_base,
- MX35_3DS_CAMERA_BUF_SIZE,
- DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
-
- if (!(dma & DMA_MEMORY_MAP))
- goto err;
-
- ret = platform_device_add(pdev);
- if (ret)
-err:
- platform_device_put(pdev);
-
- return ret;
-}
-
-static struct i2c_board_info mx35_3ds_i2c_camera = {
- I2C_BOARD_INFO("ov2640", 0x30),
-};
-
-static struct soc_camera_link iclink_ov2640 = {
- .bus_id = 0,
- .board_info = &mx35_3ds_i2c_camera,
- .i2c_adapter_id = 0,
- .power = NULL,
-};
-
-static struct platform_device mx35_3ds_ov2640 = {
- .name = "soc-camera-pdrv",
- .id = 0,
- .dev = {
- .platform_data = &iclink_ov2640,
- },
-};
-
static struct regulator_consumer_supply sw1_consumers[] = {
{
.supply = "cpu_vcc",
REGULATOR_SUPPLY("VDDA", "0-000a"),
};
-static struct regulator_consumer_supply vaudio_consumers[] = {
- REGULATOR_SUPPLY("cmos_vio", "soc-camera-pdrv.0"),
-};
-
static struct regulator_init_data sw1_init = {
.constraints = {
.name = "SW1",
}
};
-static struct regulator_init_data vaudio_init = {
- .constraints = {
- .name = "VAUDIO",
- .min_uV = 2300000,
- .max_uV = 3000000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
- .boot_on = 1
- },
- .num_consumer_supplies = ARRAY_SIZE(vaudio_consumers),
- .consumer_supplies = vaudio_consumers,
-};
-
static struct regulator_init_data vcam_init = {
.constraints = {
.name = "VCAM",
{ .id = MC13892_VDIG, .init_data = &vdig_init },
{ .id = MC13892_VUSB2, .init_data = &vusb2_init },
{ .id = MC13892_VVIDEO, .init_data = &vvideo_init },
- { .id = MC13892_VAUDIO, .init_data = &vaudio_init },
{ .id = MC13892_VCAM, .init_data = &vcam_init },
{ .id = MC13892_VGEN1, .init_data = &vgen1_init },
{ .id = MC13892_VGEN2, .init_data = &vgen2_init },
0, i2c_devices_3ds, ARRAY_SIZE(i2c_devices_3ds));
imx35_add_ipu_core();
- platform_device_register(&mx35_3ds_ov2640);
- imx35_3ds_init_camera();
}
static void __init mx35_3ds_late_init(void)
mx35_clocks_init();
}
-static void __init mx35_3ds_reserve(void)
-{
- /* reserve MX35_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
- mx3_camera_base = arm_memblock_steal(MX35_3DS_CAMERA_BUF_SIZE,
- MX35_3DS_CAMERA_BUF_SIZE);
-}
-
MACHINE_START(MX35_3DS, "Freescale MX35PDK")
/* Maintainer: Freescale Semiconductor, Inc */
.atag_offset = 0x100,
.init_time = mx35pdk_timer_init,
.init_machine = mx35_3ds_init,
.init_late = mx35_3ds_late_init,
- .reserve = mx35_3ds_reserve,
.restart = mxc_restart,
MACHINE_END
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/gfp.h>
-#include <linux/memblock.h>
#include <linux/regulator/machine.h>
#include <linux/regulator/fixed.h>
-#include <media/soc_camera.h>
-
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
-#include <asm/memblock.h>
#include "common.h"
#include "devices-imx31.h"
MX31_PIN_D3_SPL__D3_SPL,
MX31_PIN_D3_CLS__D3_CLS,
MX31_PIN_LCS0__GPIO3_23,
- /* CSI */
- IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
- MX31_PIN_CSI_D6__CSI_D6,
- MX31_PIN_CSI_D7__CSI_D7,
- MX31_PIN_CSI_D8__CSI_D8,
- MX31_PIN_CSI_D9__CSI_D9,
- MX31_PIN_CSI_D10__CSI_D10,
- MX31_PIN_CSI_D11__CSI_D11,
- MX31_PIN_CSI_D12__CSI_D12,
- MX31_PIN_CSI_D13__CSI_D13,
- MX31_PIN_CSI_D14__CSI_D14,
- MX31_PIN_CSI_D15__CSI_D15,
- MX31_PIN_CSI_HSYNC__CSI_HSYNC,
- MX31_PIN_CSI_MCLK__CSI_MCLK,
- MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
- MX31_PIN_CSI_VSYNC__CSI_VSYNC,
/* GPIO */
IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
/* OTG */
.flags = AT24_FLAG_ADDR16,
};
-static int pcm037_camera_power(struct device *dev, int on)
-{
- /* disable or enable the camera in X7 or X8 PCM970 connector */
- gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
- return 0;
-}
-
-static struct i2c_board_info pcm037_i2c_camera[] = {
- {
- I2C_BOARD_INFO("mt9t031", 0x5d),
- }, {
- I2C_BOARD_INFO("mt9v022", 0x48),
- },
-};
-
-static struct soc_camera_link iclink_mt9v022 = {
- .bus_id = 0, /* Must match with the camera ID */
- .board_info = &pcm037_i2c_camera[1],
- .i2c_adapter_id = 2,
-};
-
-static struct soc_camera_link iclink_mt9t031 = {
- .bus_id = 0, /* Must match with the camera ID */
- .power = pcm037_camera_power,
- .board_info = &pcm037_i2c_camera[0],
- .i2c_adapter_id = 2,
-};
-
static struct i2c_board_info pcm037_i2c_devices[] = {
{
I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
}
};
-static struct platform_device pcm037_mt9t031 = {
- .name = "soc-camera-pdrv",
- .id = 0,
- .dev = {
- .platform_data = &iclink_mt9t031,
- },
-};
-
-static struct platform_device pcm037_mt9v022 = {
- .name = "soc-camera-pdrv",
- .id = 1,
- .dev = {
- .platform_data = &iclink_mt9v022,
- },
-};
-
/* Not connected by default */
#ifdef PCM970_SDHC_RW_SWITCH
static int pcm970_sdhc1_get_ro(struct device *dev)
.exit = pcm970_sdhc1_exit,
};
-struct mx3_camera_pdata camera_pdata __initdata = {
- .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
- .mclk_10khz = 2000,
-};
-
-static phys_addr_t mx3_camera_base __initdata;
-#define MX3_CAMERA_BUF_SIZE SZ_4M
-
-static int __init pcm037_init_camera(void)
-{
- int dma, ret = -ENOMEM;
- struct platform_device *pdev = imx31_alloc_mx3_camera(&camera_pdata);
-
- if (IS_ERR(pdev))
- return PTR_ERR(pdev);
-
- dma = dma_declare_coherent_memory(&pdev->dev,
- mx3_camera_base, mx3_camera_base,
- MX3_CAMERA_BUF_SIZE,
- DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
- if (!(dma & DMA_MEMORY_MAP))
- goto err;
-
- ret = platform_device_add(pdev);
- if (ret)
-err:
- platform_device_put(pdev);
-
- return ret;
-}
-
static struct platform_device *devices[] __initdata = {
&pcm037_flash,
&pcm037_sram_device,
- &pcm037_mt9t031,
- &pcm037_mt9v022,
};
static const struct fb_videomode fb_modedb[] = {
mx31_clocks_init(26000000);
}
-static void __init pcm037_reserve(void)
-{
- /* reserve 4 MiB for mx3-camera */
- mx3_camera_base = arm_memblock_steal(MX3_CAMERA_BUF_SIZE,
- MX3_CAMERA_BUF_SIZE);
-}
-
static void __init pcm037_init_late(void)
{
int ret;
imx31_add_mxc_mmc(0, &sdhc_pdata);
- /* CSI */
- /* Camera power: default - off */
- ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
- if (!ret)
- gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
- else
- iclink_mt9t031.power = NULL;
-
- pcm037_init_camera();
-
pcm970_sja1000_resources[1].start =
gpio_to_irq(IOMUX_TO_GPIO(IOMUX_PIN(48, 105)));
pcm970_sja1000_resources[1].end =
MACHINE_START(PCM037, "Phytec Phycore pcm037")
/* Maintainer: Pengutronix */
.atag_offset = 0x100,
- .reserve = pcm037_reserve,
.map_io = mx31_map_io,
.init_early = imx31_init_early,
.init_irq = mx31_init_irq,
#include <linux/usb/otg.h>
-#include <media/soc_camera.h>
-
#include "common.h"
#include "devices-imx31.h"
#include "ehci.h"
MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
- /* CSI */
- MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7,
- MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9,
- MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11,
- MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13,
- MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15,
- MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK,
- MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
- MX31_PIN_CSI_D4__GPIO3_4, MX31_PIN_CSI_D5__GPIO3_5,
- MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
- MX31_PIN_TXD2__GPIO1_28,
/* dsPIC resets */
MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22,
/*battery detection */
},
};
-#define TURRETCAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
-#define BASECAM_POWER IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
-#define TURRETCAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
-#define BASECAM_RST_B IOMUX_TO_GPIO(MX31_PIN_CSI_D4)
-#define CAM_CHOICE IOMUX_TO_GPIO(MX31_PIN_TXD2)
-
-static int marxbot_basecam_power(struct device *dev, int on)
-{
- gpio_set_value(BASECAM_POWER, !on);
- return 0;
-}
-
-static int marxbot_basecam_reset(struct device *dev)
-{
- gpio_set_value(BASECAM_RST_B, 0);
- udelay(100);
- gpio_set_value(BASECAM_RST_B, 1);
- return 0;
-}
-
-static struct i2c_board_info marxbot_i2c_devices[] = {
- {
- I2C_BOARD_INFO("mt9t031", 0x5d),
- },
-};
-
-static struct soc_camera_link base_iclink = {
- .bus_id = 0, /* Must match with the camera ID */
- .power = marxbot_basecam_power,
- .reset = marxbot_basecam_reset,
- .board_info = &marxbot_i2c_devices[0],
- .i2c_adapter_id = 0,
-};
-
-static struct platform_device marxbot_camera[] = {
- {
- .name = "soc-camera-pdrv",
- .id = 0,
- .dev = {
- .platform_data = &base_iclink,
- },
- },
-};
-
-static struct platform_device *marxbot_cameras[] __initdata = {
- &marxbot_camera[0],
-};
-
-static int __init marxbot_cam_init(void)
-{
- int ret = gpio_request(CAM_CHOICE, "cam-choice");
- if (ret)
- return ret;
- gpio_direction_output(CAM_CHOICE, 0);
-
- ret = gpio_request(BASECAM_RST_B, "basecam-reset");
- if (ret)
- return ret;
- gpio_direction_output(BASECAM_RST_B, 1);
- ret = gpio_request(BASECAM_POWER, "basecam-standby");
- if (ret)
- return ret;
- gpio_direction_output(BASECAM_POWER, 0);
-
- ret = gpio_request(TURRETCAM_RST_B, "turretcam-reset");
- if (ret)
- return ret;
- gpio_direction_output(TURRETCAM_RST_B, 1);
- ret = gpio_request(TURRETCAM_POWER, "turretcam-standby");
- if (ret)
- return ret;
- gpio_direction_output(TURRETCAM_POWER, 0);
-
- return 0;
-}
-
#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
spi_register_board_info(marxbot_spi_board_info,
ARRAY_SIZE(marxbot_spi_board_info));
- marxbot_cam_init();
- platform_add_devices(marxbot_cameras, ARRAY_SIZE(marxbot_cameras));
-
/* battery present pin */
gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present");
gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0));
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
-#include <media/soc_camera.h>
-
#include "board-mx31moboard.h"
#include "common.h"
#include "devices-imx31.h"
/* UART1 */
MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
- /* CSI */
- MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5,
- MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7,
- MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9,
- MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11,
- MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13,
- MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15,
- MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK,
- MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
- MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
/* ENABLES */
MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
.flags = IMXUART_HAVE_RTSCTS,
};
-#define CAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
-#define CAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
-
-static int smartbot_cam_power(struct device *dev, int on)
-{
- gpio_set_value(CAM_POWER, !on);
- return 0;
-}
-
-static int smartbot_cam_reset(struct device *dev)
-{
- gpio_set_value(CAM_RST_B, 0);
- udelay(100);
- gpio_set_value(CAM_RST_B, 1);
- return 0;
-}
-
-static struct i2c_board_info smartbot_i2c_devices[] = {
- {
- I2C_BOARD_INFO("mt9t031", 0x5d),
- },
-};
-
-static struct soc_camera_link base_iclink = {
- .bus_id = 0, /* Must match with the camera ID */
- .power = smartbot_cam_power,
- .reset = smartbot_cam_reset,
- .board_info = &smartbot_i2c_devices[0],
- .i2c_adapter_id = 0,
-};
-
-static struct platform_device smartbot_camera[] = {
- {
- .name = "soc-camera-pdrv",
- .id = 0,
- .dev = {
- .platform_data = &base_iclink,
- },
- },
-};
-
-static struct platform_device *smartbot_cameras[] __initdata = {
- &smartbot_camera[0],
-};
-
-static int __init smartbot_cam_init(void)
-{
- int ret = gpio_request(CAM_RST_B, "cam-reset");
- if (ret)
- return ret;
- gpio_direction_output(CAM_RST_B, 1);
- ret = gpio_request(CAM_POWER, "cam-standby");
- if (ret)
- return ret;
- gpio_direction_output(CAM_POWER, 0);
-
- return 0;
-}
-
static const struct fsl_usb2_platform_data usb_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
}
smartbot_resets_init();
-
- smartbot_cam_init();
- platform_add_devices(smartbot_cameras, ARRAY_SIZE(smartbot_cameras));
}
u8 root_bus_nr;
void __iomem *base;
spinlock_t conf_lock;
- char mem_space_name[16];
+ char mem_space_name[20];
struct resource res;
};
CPU_METHOD_OF_DECLARE(armada_xp_smp, "marvell,armada-xp-smp",
&armada_xp_smp_ops);
+
+#define MV98DX3236_CPU_RESUME_CTRL_REG 0x08
+#define MV98DX3236_CPU_RESUME_ADDR_REG 0x04
+
+static const struct of_device_id of_mv98dx3236_resume_table[] = {
+ {
+ .compatible = "marvell,98dx3336-resume-ctrl",
+ },
+ { /* end of list */ },
+};
+
+static int mv98dx3236_resume_set_cpu_boot_addr(int hw_cpu, void *boot_addr)
+{
+ struct device_node *np;
+ void __iomem *base;
+ WARN_ON(hw_cpu != 1);
+
+ np = of_find_matching_node(NULL, of_mv98dx3236_resume_table);
+ if (!np)
+ return -ENODEV;
+
+ base = of_io_request_and_map(np, 0, of_node_full_name(np));
+ of_node_put(np);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ writel(0, base + MV98DX3236_CPU_RESUME_CTRL_REG);
+ writel(virt_to_phys(boot_addr), base + MV98DX3236_CPU_RESUME_ADDR_REG);
+
+ iounmap(base);
+
+ return 0;
+}
+
+static int mv98dx3236_boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+ int ret, hw_cpu;
+
+ hw_cpu = cpu_logical_map(cpu);
+ set_secondary_cpu_clock(hw_cpu);
+ mv98dx3236_resume_set_cpu_boot_addr(hw_cpu,
+ armada_xp_secondary_startup);
+
+ /*
+ * This is needed to wake up CPUs in the offline state after
+ * using CPU hotplug.
+ */
+ arch_send_wakeup_ipi_mask(cpumask_of(cpu));
+
+ /*
+ * This is needed to take secondary CPUs out of reset on the
+ * initial boot.
+ */
+ ret = mvebu_cpu_reset_deassert(hw_cpu);
+ if (ret) {
+ pr_warn("unable to boot CPU: %d\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct smp_operations mv98dx3236_smp_ops __initconst = {
+ .smp_init_cpus = armada_xp_smp_init_cpus,
+ .smp_prepare_cpus = armada_xp_smp_prepare_cpus,
+ .smp_boot_secondary = mv98dx3236_boot_secondary,
+ .smp_secondary_init = armada_xp_secondary_init,
+#ifdef CONFIG_HOTPLUG_CPU
+ .cpu_die = armada_xp_cpu_die,
+ .cpu_kill = armada_xp_cpu_kill,
+#endif
+};
+
+CPU_METHOD_OF_DECLARE(mv98dx3236_smp, "marvell,98dx3236-smp",
+ &mv98dx3236_smp_ops);
* OMAP specific clock functions shared between omap1 and omap2
*/
-int __initdata mpurate;
-
-/*
- * By default we use the rate set by the bootloader.
- * You can override this with mpurate= cmdline option.
- */
-static int __init omap_clk_setup(char *str)
-{
- get_option(&str, &mpurate);
-
- if (!mpurate)
- return 1;
-
- if (mpurate < 1000)
- mpurate *= 1000000;
-
- return 1;
-}
-__setup("mpurate=", omap_clk_setup);
-
/* Used for clocks that always have same value as the parent clock */
unsigned long followparent_recalc(struct clk *clk)
{
void (*clk_disable_unused)(struct clk *clk);
};
-extern int mpurate;
-
extern int clk_init(struct clk_functions *custom_clocks);
extern void clk_preinit(struct clk *clk);
extern int clk_register(struct clk *clk);
#include <linux/platform_data/usb-omap1.h>
-void omap_otg_init(struct omap_usb_config *config);
-
#if IS_ENABLED(CONFIG_USB)
void omap1_usb_init(struct omap_usb_config *pdata);
#else
/*
- * Platform level USB initialization for FS USB OTG controller on omap1 and 24xx
+ * Platform level USB initialization for FS USB OTG controller on omap1
*
* Copyright (C) 2004 Texas Instruments, Inc.
*
#ifdef CONFIG_ARCH_OMAP_OTG
-void __init
+static void __init
omap_otg_init(struct omap_usb_config *config)
{
u32 syscon;
int alt_pingroup = 0;
+ u16 w;
/* NOTE: no bus or clock setup (yet?) */
if (config->otg)
syscon |= OTG_EN;
#endif
- if (cpu_class_is_omap1())
- pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
- omap_readl(USB_TRANSCEIVER_CTRL));
+ pr_debug("USB_TRANSCEIVER_CTRL = %03x\n",
+ omap_readl(USB_TRANSCEIVER_CTRL));
pr_debug("OTG_SYSCON_2 = %08x\n", omap_readl(OTG_SYSCON_2));
omap_writel(syscon, OTG_SYSCON_2);
printk("USB: hmc %d", config->hmc_mode);
if (!alt_pingroup)
- printk(", usb2 alt %d wires", config->pins[2]);
+ pr_cont(", usb2 alt %d wires", config->pins[2]);
else if (config->pins[0])
- printk(", usb0 %d wires%s", config->pins[0],
+ pr_cont(", usb0 %d wires%s", config->pins[0],
is_usb0_device(config) ? " (dev)" : "");
if (config->pins[1])
- printk(", usb1 %d wires", config->pins[1]);
+ pr_cont(", usb1 %d wires", config->pins[1]);
if (!alt_pingroup && config->pins[2])
- printk(", usb2 %d wires", config->pins[2]);
+ pr_cont(", usb2 %d wires", config->pins[2]);
if (config->otg)
- printk(", Mini-AB on usb%d", config->otg - 1);
- printk("\n");
+ pr_cont(", Mini-AB on usb%d", config->otg - 1);
+ pr_cont("\n");
- if (cpu_class_is_omap1()) {
- u16 w;
+ /* leave USB clocks/controllers off until needed */
+ w = omap_readw(ULPD_SOFT_REQ);
+ w &= ~SOFT_USB_CLK_REQ;
+ omap_writew(w, ULPD_SOFT_REQ);
- /* leave USB clocks/controllers off until needed */
- w = omap_readw(ULPD_SOFT_REQ);
- w &= ~SOFT_USB_CLK_REQ;
- omap_writew(w, ULPD_SOFT_REQ);
+ w = omap_readw(ULPD_CLOCK_CTRL);
+ w &= ~USB_MCLK_EN;
+ w |= DIS_USB_PVCI_CLK;
+ omap_writew(w, ULPD_CLOCK_CTRL);
- w = omap_readw(ULPD_CLOCK_CTRL);
- w &= ~USB_MCLK_EN;
- w |= DIS_USB_PVCI_CLK;
- omap_writew(w, ULPD_CLOCK_CTRL);
- }
syscon = omap_readl(OTG_SYSCON_1);
syscon |= HST_IDLE_EN|DEV_IDLE_EN|OTG_IDLE_EN;
}
#else
-void omap_otg_init(struct omap_usb_config *config) {}
+static void omap_otg_init(struct omap_usb_config *config) {}
#endif
#if IS_ENABLED(CONFIG_USB_OMAP)
printk("USB: hmc %d", config->hmc_mode);
if (config->pins[0])
- printk(", usb0 %d wires%s", config->pins[0],
+ pr_cont(", usb0 %d wires%s", config->pins[0],
is_usb0_device(config) ? " (dev)" : "");
if (config->pins[1])
- printk(", usb1 %d wires", config->pins[1]);
+ pr_cont(", usb1 %d wires", config->pins[1]);
if (config->pins[2])
- printk(", usb2 %d wires", config->pins[2]);
- printk("\n");
+ pr_cont(", usb2 %d wires", config->pins[2]);
+ pr_cont("\n");
/* use DPLL for 48 MHz function clock */
pr_debug("APLL %04x DPLL %04x REQ %04x\n", omap_readw(ULPD_APLL_CTRL),
* OMAP2+ specific clock functions
*/
-/* Private functions */
-
/* Public functions */
/**
}
}
-static int __initdata mpurate;
-
-/*
- * By default we use the rate set by the bootloader.
- * You can override this with mpurate= cmdline option.
- */
-static int __init omap_clk_setup(char *str)
-{
- get_option(&str, &mpurate);
-
- if (!mpurate)
- return 1;
-
- if (mpurate < 1000)
- mpurate *= 1000000;
-
- return 1;
-}
-__setup("mpurate=", omap_clk_setup);
-
-/**
- * omap2_clk_print_new_rates - print summary of current clock tree rates
- * @hfclkin_ck_name: clk name for the off-chip HF oscillator
- * @core_ck_name: clk name for the on-chip CORE_CLK
- * @mpu_ck_name: clk name for the ARM MPU clock
- *
- * Prints a short message to the console with the HFCLKIN oscillator
- * rate, the rate of the CORE clock, and the rate of the ARM MPU clock.
- * Called by the boot-time MPU rate switching code. XXX This is intended
- * to be handled by the OPP layer code in the near future and should be
- * removed from the clock code. No return value.
- */
-void __init omap2_clk_print_new_rates(const char *hfclkin_ck_name,
- const char *core_ck_name,
- const char *mpu_ck_name)
-{
- struct clk *hfclkin_ck, *core_ck, *mpu_ck;
- unsigned long hfclkin_rate;
-
- mpu_ck = clk_get(NULL, mpu_ck_name);
- if (WARN(IS_ERR(mpu_ck), "clock: failed to get %s.\n", mpu_ck_name))
- return;
-
- core_ck = clk_get(NULL, core_ck_name);
- if (WARN(IS_ERR(core_ck), "clock: failed to get %s.\n", core_ck_name))
- return;
-
- hfclkin_ck = clk_get(NULL, hfclkin_ck_name);
- if (WARN(IS_ERR(hfclkin_ck), "Failed to get %s.\n", hfclkin_ck_name))
- return;
-
- hfclkin_rate = clk_get_rate(hfclkin_ck);
-
- pr_info("Switched to new clocking rate (Crystal/Core/MPU): %ld.%01ld/%ld/%ld MHz\n",
- (hfclkin_rate / 1000000), ((hfclkin_rate / 100000) % 10),
- (clk_get_rate(core_ck) / 1000000),
- (clk_get_rate(mpu_ck) / 1000000));
-}
-
/**
* ti_clk_init_features - init clock features struct for the SoC
*
#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
#define OMAP4XXX_EN_DPLL_LOCKED 0x7
-void omap2_clk_print_new_rates(const char *hfclkin_ck_name,
- const char *core_ck_name,
- const char *mpu_ck_name);
-
extern u16 cpu_mask;
extern const struct clkops clkops_omap2_dflt_wait;
#define DISPC_CONTROL3 0x0848
#define DISPC_IRQSTATUS 0x0018
-#define DSS_SYSCONFIG 0x10
-#define DSS_SYSSTATUS 0x14
#define DSS_CONTROL 0x40
#define DSS_SDI_CONTROL 0x44
#define DSS_PLL_CONTROL 0x48
},
};
-struct omap_dss_hwmod_data {
- const char *oh_name;
- const char *dev_name;
- const int id;
-};
-
-static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initconst = {
- { "dss_core", "omapdss_dss", -1 },
- { "dss_dispc", "omapdss_dispc", -1 },
- { "dss_rfbi", "omapdss_rfbi", -1 },
- { "dss_venc", "omapdss_venc", -1 },
-};
-
-static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initconst = {
- { "dss_core", "omapdss_dss", -1 },
- { "dss_dispc", "omapdss_dispc", -1 },
- { "dss_rfbi", "omapdss_rfbi", -1 },
- { "dss_venc", "omapdss_venc", -1 },
- { "dss_dsi1", "omapdss_dsi", 0 },
-};
-
-static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initconst = {
- { "dss_core", "omapdss_dss", -1 },
- { "dss_dispc", "omapdss_dispc", -1 },
- { "dss_rfbi", "omapdss_rfbi", -1 },
- { "dss_dsi1", "omapdss_dsi", 0 },
- { "dss_dsi2", "omapdss_dsi", 1 },
- { "dss_hdmi", "omapdss_hdmi", -1 },
-};
-
#define OMAP4_DSIPHY_SYSCON_OFFSET 0x78
static struct regmap *omap4_dsi_mux_syscon;
return omap_pm_set_min_bus_tput(dev, OCP_INITIATOR_AGENT, tput);
}
-static struct platform_device *create_dss_pdev(const char *pdev_name,
- int pdev_id, const char *oh_name, void *pdata, int pdata_len,
- struct platform_device *parent)
-{
- struct platform_device *pdev;
- struct omap_device *od;
- struct omap_hwmod *ohs[1];
- struct omap_hwmod *oh;
- int r;
-
- oh = omap_hwmod_lookup(oh_name);
- if (!oh) {
- pr_err("Could not look up %s\n", oh_name);
- r = -ENODEV;
- goto err;
- }
-
- pdev = platform_device_alloc(pdev_name, pdev_id);
- if (!pdev) {
- pr_err("Could not create pdev for %s\n", pdev_name);
- r = -ENOMEM;
- goto err;
- }
-
- if (parent != NULL)
- pdev->dev.parent = &parent->dev;
-
- if (pdev->id != -1)
- dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
- else
- dev_set_name(&pdev->dev, "%s", pdev->name);
-
- ohs[0] = oh;
- od = omap_device_alloc(pdev, ohs, 1);
- if (IS_ERR(od)) {
- pr_err("Could not alloc omap_device for %s\n", pdev_name);
- r = -ENOMEM;
- goto err;
- }
-
- r = platform_device_add_data(pdev, pdata, pdata_len);
- if (r) {
- pr_err("Could not set pdata for %s\n", pdev_name);
- goto err;
- }
-
- r = omap_device_register(pdev);
- if (r) {
- pr_err("Could not register omap_device for %s\n", pdev_name);
- goto err;
- }
-
- return pdev;
-
-err:
- return ERR_PTR(r);
-}
-
-static struct platform_device *create_simple_dss_pdev(const char *pdev_name,
- int pdev_id, void *pdata, int pdata_len,
- struct platform_device *parent)
-{
- struct platform_device *pdev;
- int r;
-
- pdev = platform_device_alloc(pdev_name, pdev_id);
- if (!pdev) {
- pr_err("Could not create pdev for %s\n", pdev_name);
- r = -ENOMEM;
- goto err;
- }
-
- if (parent != NULL)
- pdev->dev.parent = &parent->dev;
-
- if (pdev->id != -1)
- dev_set_name(&pdev->dev, "%s.%d", pdev->name, pdev->id);
- else
- dev_set_name(&pdev->dev, "%s", pdev->name);
-
- r = platform_device_add_data(pdev, pdata, pdata_len);
- if (r) {
- pr_err("Could not set pdata for %s\n", pdev_name);
- goto err;
- }
-
- r = platform_device_add(pdev);
- if (r) {
- pr_err("Could not register platform_device for %s\n", pdev_name);
- goto err;
- }
-
- return pdev;
-
-err:
- return ERR_PTR(r);
-}
-
static enum omapdss_version __init omap_display_get_version(void)
{
if (cpu_is_omap24xx())
return OMAPDSS_VER_UNKNOWN;
}
-int __init omap_display_init(struct omap_dss_board_info *board_data)
-{
- int r = 0;
- struct platform_device *pdev;
- int i, oh_count;
- const struct omap_dss_hwmod_data *curr_dss_hwmod;
- struct platform_device *dss_pdev;
- enum omapdss_version ver;
-
- /* create omapdss device */
-
- ver = omap_display_get_version();
-
- if (ver == OMAPDSS_VER_UNKNOWN) {
- pr_err("DSS not supported on this SoC\n");
- return -ENODEV;
- }
-
- board_data->version = ver;
- board_data->dsi_enable_pads = omap_dsi_enable_pads;
- board_data->dsi_disable_pads = omap_dsi_disable_pads;
- board_data->set_min_bus_tput = omap_dss_set_min_bus_tput;
-
- omap_display_device.dev.platform_data = board_data;
-
- r = platform_device_register(&omap_display_device);
- if (r < 0) {
- pr_err("Unable to register omapdss device\n");
- return r;
- }
-
- /* create devices for dss hwmods */
-
- if (cpu_is_omap24xx()) {
- curr_dss_hwmod = omap2_dss_hwmod_data;
- oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
- } else if (cpu_is_omap34xx()) {
- curr_dss_hwmod = omap3_dss_hwmod_data;
- oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
- } else {
- curr_dss_hwmod = omap4_dss_hwmod_data;
- oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
- }
-
- /*
- * First create the pdev for dss_core, which is used as a parent device
- * by the other dss pdevs. Note: dss_core has to be the first item in
- * the hwmod list.
- */
- dss_pdev = create_dss_pdev(curr_dss_hwmod[0].dev_name,
- curr_dss_hwmod[0].id,
- curr_dss_hwmod[0].oh_name,
- board_data, sizeof(*board_data),
- NULL);
-
- if (IS_ERR(dss_pdev)) {
- pr_err("Could not build omap_device for %s\n",
- curr_dss_hwmod[0].oh_name);
-
- return PTR_ERR(dss_pdev);
- }
-
- for (i = 1; i < oh_count; i++) {
- pdev = create_dss_pdev(curr_dss_hwmod[i].dev_name,
- curr_dss_hwmod[i].id,
- curr_dss_hwmod[i].oh_name,
- board_data, sizeof(*board_data),
- dss_pdev);
-
- if (IS_ERR(pdev)) {
- pr_err("Could not build omap_device for %s\n",
- curr_dss_hwmod[i].oh_name);
-
- return PTR_ERR(pdev);
- }
- }
-
- /* Create devices for DPI and SDI */
-
- pdev = create_simple_dss_pdev("omapdss_dpi", 0,
- board_data, sizeof(*board_data), dss_pdev);
- if (IS_ERR(pdev)) {
- pr_err("Could not build platform_device for omapdss_dpi\n");
- return PTR_ERR(pdev);
- }
-
- if (cpu_is_omap34xx()) {
- pdev = create_simple_dss_pdev("omapdss_sdi", 0,
- board_data, sizeof(*board_data), dss_pdev);
- if (IS_ERR(pdev)) {
- pr_err("Could not build platform_device for omapdss_sdi\n");
- return PTR_ERR(pdev);
- }
- }
-
- /* create DRM device */
- r = omap_init_drm();
- if (r < 0) {
- pr_err("Unable to register omapdrm device\n");
- return r;
- }
-
- /* create vrfb device */
- r = omap_init_vrfb();
- if (r < 0) {
- pr_err("Unable to register omapvrfb device\n");
- return r;
- }
-
- /* create FB device */
- r = omap_init_fb();
- if (r < 0) {
- pr_err("Unable to register omapfb device\n");
- return r;
- }
-
- /* create V4L2 display device */
- r = omap_init_vout();
- if (r < 0) {
- pr_err("Unable to register omap_vout device\n");
- return r;
- }
-
- return 0;
-}
-
static void dispc_disable_outputs(void)
{
u32 v, irq_mask = 0;
"ti,dra7-dss",
};
-struct device_node * __init omapdss_find_dss_of_node(void)
+static struct device_node * __init omapdss_find_dss_of_node(void)
{
struct device_node *node;
int i;
int omap_init_fb(void);
int omap_init_vout(void);
-struct device_node * __init omapdss_find_dss_of_node(void);
-
-struct omap_dss_board_info;
-
-/* Init with the board info */
-int omap_display_init(struct omap_dss_board_info *board_data);
-
#endif
return 0;
}
+/**
+ * omap_hwmod_setup_earlycon_flags - set up flags for early console
+ *
+ * Enable DEBUG_OMAPUART_FLAGS for uart hwmod that is being used as
+ * early concole so that hwmod core doesn't reset and keep it in idle
+ * that specific uart.
+ */
+#ifdef CONFIG_SERIAL_EARLYCON
+static void __init omap_hwmod_setup_earlycon_flags(void)
+{
+ struct device_node *np;
+ struct omap_hwmod *oh;
+ const char *uart;
+
+ np = of_find_node_by_path("/chosen");
+ if (np) {
+ uart = of_get_property(np, "stdout-path", NULL);
+ if (uart) {
+ np = of_find_node_by_path(uart);
+ if (np) {
+ uart = of_get_property(np, "ti,hwmods", NULL);
+ oh = omap_hwmod_lookup(uart);
+ if (oh)
+ oh->flags |= DEBUG_OMAPUART_FLAGS;
+ }
+ }
+ }
+}
+#endif
+
/**
* omap_hwmod_setup_all - set up all registered IP blocks
*
_ensure_mpu_hwmod_is_setup(NULL);
omap_hwmod_for_each(_init, NULL);
+#ifdef CONFIG_SERIAL_EARLYCON
+ omap_hwmod_setup_earlycon_flags();
+#endif
omap_hwmod_for_each(_setup, NULL);
return 0;
};
#endif /* CONFIG_MACH_EZX_E2 */
-#ifdef CONFIG_MACH_EZX_A780
-/* gpio_keys */
-static struct gpio_keys_button a780_buttons[] = {
- [0] = {
- .code = SW_LID,
- .gpio = GPIO12_A780_FLIP_LID,
- .active_low = 0,
- .desc = "A780 flip lid",
- .type = EV_SW,
- .wakeup = 1,
- },
-};
-
-static struct gpio_keys_platform_data a780_gpio_keys_platform_data = {
- .buttons = a780_buttons,
- .nbuttons = ARRAY_SIZE(a780_buttons),
-};
-
-static struct platform_device a780_gpio_keys = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &a780_gpio_keys_platform_data,
- },
-};
-
+#if defined(CONFIG_MACH_EZX_A780) || defined(CONFIG_MACH_EZX_A910)
/* camera */
static struct regulator_consumer_supply camera_dummy_supplies[] = {
REGULATOR_SUPPLY("vdd", "0-005d"),
.platform_data = &camera_dummy_config,
},
};
+#endif
+
+#ifdef CONFIG_MACH_EZX_A780
+/* gpio_keys */
+static struct gpio_keys_button a780_buttons[] = {
+ [0] = {
+ .code = SW_LID,
+ .gpio = GPIO12_A780_FLIP_LID,
+ .active_low = 0,
+ .desc = "A780 flip lid",
+ .type = EV_SW,
+ .wakeup = 1,
+ },
+};
+
+static struct gpio_keys_platform_data a780_gpio_keys_platform_data = {
+ .buttons = a780_buttons,
+ .nbuttons = ARRAY_SIZE(a780_buttons),
+};
+
+static struct platform_device a780_gpio_keys = {
+ .name = "gpio-keys",
+ .id = -1,
+ .dev = {
+ .platform_data = &a780_gpio_keys_platform_data,
+ },
+};
+
+/* camera */
static int a780_camera_reset(struct device *dev)
{
gpio_set_value(GPIO19_GEN1_CAM_RST, 0);
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/leds.h>
#include <linux/platform_device.h>
#include <linux/fb.h>
/* table of ISA irq nos to the relevant mask... zero means
* the irq is not implemented
*/
-static unsigned char bast_pc104_irqmasks[] = {
+static const unsigned char bast_pc104_irqmasks[] = {
0, /* 0 */
0, /* 1 */
0, /* 2 */
0, /* 15 */
};
-static unsigned char bast_pc104_irqs[] = { 3, 5, 7, 10 };
+static const unsigned char bast_pc104_irqs[] = { 3, 5, 7, 10 };
static void
bast_pc104_mask(struct irq_data *data)
return 0;
}
-static unsigned int tacc_tab[] = {
+static const unsigned int tacc_tab[] = {
[0] = 1,
[1] = 2,
[2] = 3,
}
/* mapping of interrupts to parts of the wakeup mask */
-static struct samsung_wakeup_mask wake_irqs[] = {
+static const struct samsung_wakeup_mask wake_irqs[] = {
{ .irq = IRQ_RTC, .bit = S3C2412_PWRCFG_RTC_MASKIRQ, },
};
#include "watchdog-reset.h"
/* External clock frequency */
-static unsigned long xtal_f = 12000000, xusbxti_f = 48000000;
+static unsigned long xtal_f __ro_after_init = 12000000;
+static unsigned long xusbxti_f __ro_after_init = 48000000;
void __init s3c64xx_set_xtal_freq(unsigned long freq)
{
static struct s3c_audio_pdata i2s0_pdata = {
.cfg_gpio = s3c64xx_i2s_cfg_gpio,
- .dma_filter = pl08x_filter_id,
- .dma_playback = DMACH_I2S0_OUT,
- .dma_capture = DMACH_I2S0_IN,
};
struct platform_device s3c64xx_device_iis0 = {
static struct s3c_audio_pdata i2s1_pdata = {
.cfg_gpio = s3c64xx_i2s_cfg_gpio,
- .dma_filter = pl08x_filter_id,
- .dma_playback = DMACH_I2S1_OUT,
- .dma_capture = DMACH_I2S1_IN,
};
struct platform_device s3c64xx_device_iis1 = {
static struct s3c_audio_pdata i2sv4_pdata = {
.cfg_gpio = s3c64xx_i2s_cfg_gpio,
- .dma_filter = pl08x_filter_id,
- .dma_playback = DMACH_HSI_I2SV40_TX,
- .dma_capture = DMACH_HSI_I2SV40_RX,
.type = {
.quirks = QUIRK_PRI_6CHAN,
},
static struct s3c_audio_pdata s3c_pcm0_pdata = {
.cfg_gpio = s3c64xx_pcm_cfg_gpio,
- .dma_filter = pl08x_filter_id,
- .dma_capture = DMACH_PCM0_RX,
- .dma_playback = DMACH_PCM0_TX,
};
struct platform_device s3c64xx_device_pcm0 = {
static struct s3c_audio_pdata s3c_pcm1_pdata = {
.cfg_gpio = s3c64xx_pcm_cfg_gpio,
- .dma_filter = pl08x_filter_id,
- .dma_playback = DMACH_PCM1_TX,
- .dma_capture = DMACH_PCM1_RX,
};
struct platform_device s3c64xx_device_pcm1 = {
};
static struct s3c_audio_pdata s3c_ac97_pdata = {
- .dma_playback = DMACH_AC97_PCMOUT,
- .dma_filter = pl08x_filter_id,
- .dma_capture = DMACH_AC97_PCMIN,
- .dma_capture_mic = DMACH_AC97_MICIN,
};
static u64 s3c64xx_ac97_dmamask = DMA_BIT_MASK(32);
}
/* mapping of interrupts to parts of the wakeup mask */
-static struct samsung_wakeup_mask wake_irqs[] = {
+static const struct samsung_wakeup_mask wake_irqs[] = {
{ .irq = IRQ_RTC_ALARM, .bit = S3C64XX_PWRCFG_RTC_ALARM_DISABLE, },
{ .irq = IRQ_RTC_TIC, .bit = S3C64XX_PWRCFG_RTC_TICK_DISABLE, },
{ .irq = IRQ_PENDN, .bit = S3C64XX_PWRCFG_TS_DISABLE, },
int bit;
} apmu_cpus[NR_CPUS];
-#define WUPCR_OFFS 0x10
-#define PSTR_OFFS 0x40
-#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n)))
+#define WUPCR_OFFS 0x10 /* Wake Up Control Register */
+#define PSTR_OFFS 0x40 /* Power Status Register */
+#define CPUNCR_OFFS(n) (0x100 + (0x10 * (n)))
+ /* CPUn Power Status Control Register */
+#define DBGRCR_OFFS 0x180 /* Debug Resource Reset Control Reg. */
+
+/* Power Status Register */
+#define CPUNST(r, n) (((r) >> (n * 4)) & 3) /* CPUn Status Bit */
+#define CPUST_RUN 0 /* Run Mode */
+#define CPUST_STANDBY 3 /* CoreStandby Mode */
+
+/* Debug Resource Reset Control Register */
+#define DBGCPUREN BIT(24) /* CPU Other Reset Request Enable */
+#define DBGCPUNREN(n) BIT((n) + 20) /* CPUn Reset Request Enable */
+#define DBGCPUPREN BIT(19) /* CPU Peripheral Reset Req. Enable */
static int __maybe_unused apmu_power_on(void __iomem *p, int bit)
{
int k;
for (k = 0; k < 1000; k++) {
- if (((readl_relaxed(p + PSTR_OFFS) >> (bit * 4)) & 0x03) == 3)
+ if (CPUNST(readl_relaxed(p + PSTR_OFFS), bit) == CPUST_STANDBY)
return 1;
mdelay(1);
#ifdef CONFIG_SMP
static void apmu_init_cpu(struct resource *res, int cpu, int bit)
{
+ u32 x;
+
if ((cpu >= ARRAY_SIZE(apmu_cpus)) || apmu_cpus[cpu].iomem)
return;
apmu_cpus[cpu].bit = bit;
pr_debug("apmu ioremap %d %d %pr\n", cpu, bit, res);
+
+ /* Setup for debug mode */
+ x = readl(apmu_cpus[cpu].iomem + DBGRCR_OFFS);
+ x |= DBGCPUREN | DBGCPUNREN(bit) | DBGCPUPREN;
+ writel(x, apmu_cpus[cpu].iomem + DBGRCR_OFFS);
}
static void apmu_parse_cfg(void (*fn)(struct resource *res, int cpu, int bit),
rcar_gen2_pm_init();
}
-static int shmobile_smp_apmu_boot_secondary_md21(unsigned int cpu,
- struct task_struct *idle)
-{
- /* Error out when hardware debug mode is enabled */
- if (rcar_gen2_read_mode_pins() & BIT(21)) {
- pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu);
- return -ENOTSUPP;
- }
-
- return shmobile_smp_apmu_boot_secondary(cpu, idle);
-}
-
static struct smp_operations apmu_smp_ops __initdata = {
.smp_prepare_cpus = shmobile_smp_apmu_prepare_cpus_dt,
- .smp_boot_secondary = shmobile_smp_apmu_boot_secondary_md21,
+ .smp_boot_secondary = shmobile_smp_apmu_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_can_disable = shmobile_smp_cpu_can_disable,
.cpu_die = shmobile_smp_apmu_cpu_die,
/* RST */
#define RST 0xe6160000
-#define CA15BAR 0x0020
-#define CA7BAR 0x0030
-#define CA15RESCNT 0x0040
-#define CA7RESCNT 0x0044
+
+#define CA15BAR 0x0020 /* CA15 Boot Address Register */
+#define CA7BAR 0x0030 /* CA7 Boot Address Register */
+#define CA15RESCNT 0x0040 /* CA15 Reset Control Register */
+#define CA7RESCNT 0x0044 /* CA7 Reset Control Register */
+
+/* SYS Boot Address Register */
+#define SBAR_BAREN BIT(4) /* SBAR is valid */
+
+/* Reset Control Registers */
+#define CA15RESCNT_CODE 0xa5a50000
+#define CA15RESCNT_CPUS 0xf /* CPU0-3 */
+#define CA7RESCNT_CODE 0x5a5a0000
+#define CA7RESCNT_CPUS 0xf /* CPU0-3 */
+
/* On-chip RAM */
#define ICRAM1 0xe63c0000 /* Inter Connect RAM1 (4 KiB) */
+static inline u32 phys_to_sbar(phys_addr_t addr)
+{
+ return (addr >> 8) & 0xfffffc00;
+}
+
/* SYSC */
#define SYSCIER 0x0c
#define SYSCIMR 0x10
/* setup reset vectors */
p = ioremap_nocache(RST, 0x63);
- bar = (boot_vector_addr >> 8) & 0xfffffc00;
+ bar = phys_to_sbar(boot_vector_addr);
if (has_a15) {
writel_relaxed(bar, p + CA15BAR);
- writel_relaxed(bar | 0x10, p + CA15BAR);
+ writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
/* de-assert reset for CA15 CPUs */
- writel_relaxed((readl_relaxed(p + CA15RESCNT) & ~0x0f) |
- 0xa5a50000, p + CA15RESCNT);
+ writel_relaxed((readl_relaxed(p + CA15RESCNT) &
+ ~CA15RESCNT_CPUS) | CA15RESCNT_CODE,
+ p + CA15RESCNT);
}
if (has_a7) {
writel_relaxed(bar, p + CA7BAR);
- writel_relaxed(bar | 0x10, p + CA7BAR);
+ writel_relaxed(bar | SBAR_BAREN, p + CA7BAR);
/* de-assert reset for CA7 CPUs */
- writel_relaxed((readl_relaxed(p + CA7RESCNT) & ~0x0f) |
- 0x5a5a0000, p + CA7RESCNT);
+ writel_relaxed((readl_relaxed(p + CA7RESCNT) &
+ ~CA7RESCNT_CPUS) | CA7RESCNT_CODE,
+ p + CA7RESCNT);
}
iounmap(p);
#define __ASM_RCAR_GEN2_H__
void rcar_gen2_timer_init(void);
-#define MD(nr) BIT(nr)
-u32 rcar_gen2_read_mode_pins(void);
void rcar_gen2_reserve(void);
void rcar_gen2_pm_init(void);
#include "common.h"
#include "rcar-gen2.h"
-#define MODEMR 0xe6160060
-
-u32 rcar_gen2_read_mode_pins(void)
-{
- static u32 mode;
- static bool mode_valid;
-
- if (!mode_valid) {
- void __iomem *modemr = ioremap_nocache(MODEMR, 4);
- BUG_ON(!modemr);
- mode = ioread32(modemr);
- iounmap(modemr);
- mode_valid = true;
- }
-
- return mode;
-}
-
static unsigned int __init get_extal_freq(void)
{
struct device_node *cpg, *extal;
rcar_gen2_pm_init();
}
-static int r8a7791_smp_boot_secondary(unsigned int cpu,
- struct task_struct *idle)
-{
- /* Error out when hardware debug mode is enabled */
- if (rcar_gen2_read_mode_pins() & BIT(21)) {
- pr_warn("Unable to boot CPU%u when MD21 is set\n", cpu);
- return -ENOTSUPP;
- }
-
- return shmobile_smp_apmu_boot_secondary(cpu, idle);
-}
-
const struct smp_operations r8a7791_smp_ops __initconst = {
.smp_prepare_cpus = r8a7791_smp_prepare_cpus,
- .smp_boot_secondary = r8a7791_smp_boot_secondary,
+ .smp_boot_secondary = shmobile_smp_apmu_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_can_disable = shmobile_smp_cpu_can_disable,
.cpu_die = shmobile_smp_apmu_cpu_die,
"allwinner,sun8i-a23",
"allwinner,sun8i-a33",
"allwinner,sun8i-a83t",
+ "allwinner,sun8i-h2-plus",
"allwinner,sun8i-h3",
+ "allwinner,sun8i-v3s",
NULL,
};
#include "board.h"
-static struct property_entry __initdata wifi_rfkill_prop[] = {
+static struct property_entry wifi_rfkill_prop[] __initdata = {
PROPERTY_ENTRY_STRING("name", "wifi_rfkill"),
PROPERTY_ENTRY_STRING("type", "wlan"),
{ },
obj-y := pm.o
obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o
-obj-$(CONFIG_MACH_MOP500) += board-mop500-audio.o
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
obj-$(CONFIG_PM_GENERIC_DOMAINS) += pm_domains.o
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms: GNU General Public License (GPL), version 2
- */
-
-#include <linux/platform_device.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/platform_data/dma-ste-dma40.h>
-
-#include <linux/platform_data/asoc-ux500-msp.h>
-
-#include "ste-dma40-db8500.h"
-#include "board-mop500.h"
-
-static struct stedma40_chan_cfg msp0_dma_rx = {
- .high_priority = true,
- .dir = DMA_DEV_TO_MEM,
- .dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
-};
-
-static struct stedma40_chan_cfg msp0_dma_tx = {
- .high_priority = true,
- .dir = DMA_MEM_TO_DEV,
- .dev_type = DB8500_DMA_DEV31_MSP0_SLIM0_CH0,
-};
-
-struct msp_i2s_platform_data msp0_platform_data = {
- .id = 0,
- .msp_i2s_dma_rx = &msp0_dma_rx,
- .msp_i2s_dma_tx = &msp0_dma_tx,
-};
-
-static struct stedma40_chan_cfg msp1_dma_rx = {
- .high_priority = true,
- .dir = DMA_DEV_TO_MEM,
- .dev_type = DB8500_DMA_DEV30_MSP3,
-};
-
-static struct stedma40_chan_cfg msp1_dma_tx = {
- .high_priority = true,
- .dir = DMA_MEM_TO_DEV,
- .dev_type = DB8500_DMA_DEV30_MSP1,
-};
-
-struct msp_i2s_platform_data msp1_platform_data = {
- .id = 1,
- .msp_i2s_dma_rx = NULL,
- .msp_i2s_dma_tx = &msp1_dma_tx,
-};
-
-static struct stedma40_chan_cfg msp2_dma_rx = {
- .high_priority = true,
- .dir = DMA_DEV_TO_MEM,
- .dev_type = DB8500_DMA_DEV14_MSP2,
-};
-
-static struct stedma40_chan_cfg msp2_dma_tx = {
- .high_priority = true,
- .dir = DMA_MEM_TO_DEV,
- .dev_type = DB8500_DMA_DEV14_MSP2,
- .use_fixed_channel = true,
- .phy_channel = 1,
-};
-
-struct msp_i2s_platform_data msp2_platform_data = {
- .id = 2,
- .msp_i2s_dma_rx = &msp2_dma_rx,
- .msp_i2s_dma_tx = &msp2_dma_tx,
-};
-
-struct msp_i2s_platform_data msp3_platform_data = {
- .id = 3,
- .msp_i2s_dma_rx = &msp1_dma_rx,
- .msp_i2s_dma_tx = NULL,
-};
+++ /dev/null
-/*
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License terms: GNU General Public License (GPL) version 2
- */
-
-#ifndef __BOARD_MOP500_H
-#define __BOARD_MOP500_H
-
-#include <linux/platform_data/asoc-ux500-msp.h>
-
-extern struct msp_i2s_platform_data msp0_platform_data;
-extern struct msp_i2s_platform_data msp1_platform_data;
-extern struct msp_i2s_platform_data msp2_platform_data;
-extern struct msp_i2s_platform_data msp3_platform_data;
-
-#endif
#include <linux/init.h>
#include <linux/device.h>
#include <linux/amba/bus.h>
-#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include "setup.h"
-#include "board-mop500.h"
#include "db8500-regs.h"
static int __init ux500_l2x0_unlock(void)
static struct of_dev_auxdata u8500_auxdata_lookup[] __initdata = {
/* Requires call-back bindings. */
OF_DEV_AUXDATA("arm,cortex-a9-pmu", 0, "arm-pmu", &db8500_pmu_platdata),
- /* Requires DMA bindings. */
- OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80123000,
- "ux500-msp-i2s.0", &msp0_platform_data),
- OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80124000,
- "ux500-msp-i2s.1", &msp1_platform_data),
- OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80117000,
- "ux500-msp-i2s.2", &msp2_platform_data),
- OF_DEV_AUXDATA("stericsson,ux500-msp-i2s", 0x80125000,
- "ux500-msp-i2s.3", &msp3_platform_data),
- /* Requires non-DT:able platform data. */
- OF_DEV_AUXDATA("stericsson,db8500-prcmu", 0x80157000, "db8500-prcmu", NULL),
- OF_DEV_AUXDATA("stericsson,ux500-cryp", 0xa03cb000, "cryp1", NULL),
- OF_DEV_AUXDATA("stericsson,ux500-hash", 0xa03c2000, "hash1", NULL),
- OF_DEV_AUXDATA("stericsson,snd-soc-mop500", 0, "snd-soc-mop500.0",
- NULL),
{},
};
#define UX500_CPU1_JUMPADDR_OFFSET 0x1FF4
#define UX500_CPU1_WAKEMAGIC_OFFSET 0x1FF0
-static void wakeup_secondary(void)
+static void __iomem *backupram;
+
+static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np;
- static void __iomem *backupram;
+ static void __iomem *scu_base;
+ unsigned int ncores;
+ int i;
np = of_find_compatible_node(NULL, NULL, "ste,dbx500-backupram");
if (!np) {
return;
}
- /*
- * write the address of secondary startup into the backup ram register
- * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
- * backup ram register at offset 0x1FF0, which is what boot rom code
- * is waiting for. This will wake up the secondary core from WFE.
- */
- writel(virt_to_phys(secondary_startup),
- backupram + UX500_CPU1_JUMPADDR_OFFSET);
- writel(0xA1FEED01,
- backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
-
- /* make sure write buffer is drained */
- mb();
- iounmap(backupram);
-}
-
-static void __init ux500_smp_prepare_cpus(unsigned int max_cpus)
-{
- struct device_node *np;
- static void __iomem *scu_base;
- unsigned int ncores;
- int i;
-
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
if (!np) {
pr_err("No SCU base address\n");
static int ux500_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
- wakeup_secondary();
+ /*
+ * write the address of secondary startup into the backup ram register
+ * at offset 0x1FF4, then write the magic number 0xA1FEED01 to the
+ * backup ram register at offset 0x1FF0, which is what boot rom code
+ * is waiting for. This will wake up the secondary core from WFE.
+ */
+ writel(virt_to_phys(secondary_startup),
+ backupram + UX500_CPU1_JUMPADDR_OFFSET);
+ writel(0xA1FEED01,
+ backupram + UX500_CPU1_WAKEMAGIC_OFFSET);
+
+ /* make sure write buffer is drained */
+ mb();
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
return 0;
}
+++ /dev/null
-/*
- * arch/arm/mach-ux500/ste_dma40_db8500.h
- * DB8500-SoC-specific configuration for DMA40
- *
- * Copyright (C) ST-Ericsson 2007-2010
- * License terms: GNU General Public License (GPL) version 2
- * Author: Per Friden <per.friden@stericsson.com>
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
- */
-#ifndef STE_DMA40_DB8500_H
-#define STE_DMA40_DB8500_H
-
-#define DB8500_DMA_NR_DEV 64
-
-/*
- * Unless otherwise specified, all channels numbers are used for
- * TX & RX, and can be used for either source or destination
- * channels.
- */
-enum dma_dev_type {
- DB8500_DMA_DEV0_SPI0 = 0,
- DB8500_DMA_DEV1_SD_MMC0 = 1,
- DB8500_DMA_DEV2_SD_MMC1 = 2,
- DB8500_DMA_DEV3_SD_MMC2 = 3,
- DB8500_DMA_DEV4_I2C1 = 4,
- DB8500_DMA_DEV5_I2C3 = 5,
- DB8500_DMA_DEV6_I2C2 = 6,
- DB8500_DMA_DEV7_I2C4 = 7, /* Only on V1 and later */
- DB8500_DMA_DEV8_SSP0 = 8,
- DB8500_DMA_DEV9_SSP1 = 9,
- DB8500_DMA_DEV10_MCDE_RX = 10, /* RX only */
- DB8500_DMA_DEV11_UART2 = 11,
- DB8500_DMA_DEV12_UART1 = 12,
- DB8500_DMA_DEV13_UART0 = 13,
- DB8500_DMA_DEV14_MSP2 = 14,
- DB8500_DMA_DEV15_I2C0 = 15,
- DB8500_DMA_DEV16_USB_OTG_IEP_AND_OEP_7_15 = 16,
- DB8500_DMA_DEV17_USB_OTG_IEP_AND_OEP_6_14 = 17,
- DB8500_DMA_DEV18_USB_OTG_IEP_AND_OEP_5_13 = 18,
- DB8500_DMA_DEV19_USB_OTG_IEP_AND_OEP_4_12 = 19,
- DB8500_DMA_DEV20_SLIM0_CH0_HSI_CH0 = 20,
- DB8500_DMA_DEV21_SLIM0_CH1_HSI_CH1 = 21,
- DB8500_DMA_DEV22_SLIM0_CH2_HSI_CH2 = 22,
- DB8500_DMA_DEV23_SLIM0_CH3_HSI_CH3 = 23,
- DB8500_DMA_DEV24_SXA0 = 24,
- DB8500_DMA_DEV25_SXA1 = 25,
- DB8500_DMA_DEV26_SXA2 = 26,
- DB8500_DMA_DEV27_SXA3 = 27,
- DB8500_DMA_DEV28_SD_MM2 = 28,
- DB8500_DMA_DEV29_SD_MM0 = 29,
- DB8500_DMA_DEV30_MSP1 = 30,
- /* On DB8500v2, MSP3 RX replaces MSP1 RX */
- DB8500_DMA_DEV30_MSP3 = 30,
- DB8500_DMA_DEV31_MSP0_SLIM0_CH0 = 31,
- DB8500_DMA_DEV32_SD_MM1 = 32,
- DB8500_DMA_DEV33_SPI2 = 33,
- DB8500_DMA_DEV34_I2C3_RX2_TX2 = 34,
- DB8500_DMA_DEV35_SPI1 = 35,
- DB8500_DMA_DEV36_USB_OTG_IEP_AND_OEP_3_11 = 36,
- DB8500_DMA_DEV37_USB_OTG_IEP_AND_OEP_2_10 = 37,
- DB8500_DMA_DEV38_USB_OTG_IEP_AND_OEP_1_9 = 38,
- DB8500_DMA_DEV39_USB_OTG_IEP_AND_OEP_8 = 39,
- DB8500_DMA_DEV40_SPI3 = 40,
- DB8500_DMA_DEV41_SD_MM3 = 41,
- DB8500_DMA_DEV42_SD_MM4 = 42,
- DB8500_DMA_DEV43_SD_MM5 = 43,
- DB8500_DMA_DEV44_SXA4 = 44,
- DB8500_DMA_DEV45_SXA5 = 45,
- DB8500_DMA_DEV46_SLIM0_CH8_SRC_SXA6 = 46,
- DB8500_DMA_DEV47_SLIM0_CH9_SRC_SXA7 = 47,
- DB8500_DMA_DEV48_CAC1 = 48,
- DB8500_DMA_DEV49_CAC1_TX_HAC1_TX = 49, /* TX only */
- DB8500_DMA_DEV50_HAC1_TX = 50, /* TX only */
- DB8500_DMA_MEMCPY_TX_0 = 51, /* TX only */
- DB8500_DMA_DEV52_SLIM0_CH4_HSI_CH4 = 52,
- DB8500_DMA_DEV53_SLIM0_CH5_HSI_CH5 = 53,
- DB8500_DMA_DEV54_SLIM0_CH6_HSI_CH6 = 54,
- DB8500_DMA_DEV55_SLIM0_CH7_HSI_CH7 = 55,
- /* 56 -> 60 are channels reserved for memcpy only */
- DB8500_DMA_DEV61_CAC0 = 61,
- DB8500_DMA_DEV62_CAC0_TX_HAC0_TX = 62, /* TX only */
- DB8500_DMA_DEV63_HAC0_TX = 63, /* TX only */
-};
-
-#endif
[1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
};
-static struct s3c_audio_pdata s3c_ac97_pdata = {
-#ifdef CONFIG_S3C24XX_DMAC
- .dma_filter = s3c24xx_dma_filter,
-#endif
- .dma_playback = (void *)DMACH_PCM_OUT,
- .dma_capture = (void *)DMACH_PCM_IN,
- .dma_capture_mic = (void *)DMACH_MIC_IN,
-};
-
struct platform_device s3c_device_ac97 = {
.name = "samsung-ac97",
.id = -1,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &s3c_ac97_pdata,
}
};
#endif /* CONFIG_CPU_S3C2440 */
[0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
};
-static struct s3c_audio_pdata s3c_iis_platdata = {
-#ifdef CONFIG_S3C24XX_DMAC
- .dma_filter = s3c24xx_dma_filter,
-#endif
- .dma_playback = (void *)DMACH_I2S_OUT,
- .dma_capture = (void *)DMACH_I2S_IN,
-};
-
struct platform_device s3c_device_iis = {
.name = "s3c24xx-iis",
.id = -1,
.dev = {
.dma_mask = &samsung_device_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &s3c_iis_platdata,
}
};
#endif /* CONFIG_PLAT_S3C24XX */
* required to be correct before we enter sleep.
*/
extern void samsung_sync_wakemask(void __iomem *reg,
- struct samsung_wakeup_mask *masks,
+ const struct samsung_wakeup_mask *masks,
int nr_masks);
#endif /* __PLAT_WAKEUP_MASK_H */
#include <plat/pm.h>
void samsung_sync_wakemask(void __iomem *reg,
- struct samsung_wakeup_mask *mask, int nr_mask)
+ const struct samsung_wakeup_mask *mask, int nr_mask)
{
struct irq_data *data;
u32 val;
return 0;
}
-static struct reset_control_ops pmu_reset_ops = {
+static const struct reset_control_ops pmu_reset_ops = {
.reset = pmu_reset_reset,
.assert = pmu_reset_assert,
.deassert = pmu_reset_deassert,
projects / linux-2.6-block.git / commitdiff