drm/amd/amdgpu: cleanup parse_cs callbacks
authorDavid (Ming Qiang) Wu <David.Wu3@amd.com>
Fri, 2 Aug 2024 18:29:41 +0000 (14:29 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 13 Aug 2024 16:13:03 +0000 (12:13 -0400)
Because gpu_addr is updated in the calling routine
(amdgpu_cs_patch_ibs()),it is removed in the callback.

Use .patch_cs_in_place instead of .parse_cs for
amdgpu_vce_ring_parse_cs_vm() as there is no need for keeping
a temporary IB, therefore ib->sa_bo is NULL and amdgpu_ib_free()
is removed.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c

index 775c09d57222a39d31e75a45dd3dc17c2a86a1ce..31fd30dcd593bad8ed0f092314720591fc5fa1be 100644 (file)
@@ -1088,7 +1088,6 @@ int amdgpu_uvd_ring_parse_cs(struct amdgpu_cs_parser *parser,
        int r;
 
        job->vm = NULL;
-       ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
 
        if (ib->length_dw % 16) {
                DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n",
index 51b045de409d0e44ecb8efdf92935b03fce40c30..74fdbf71d95b74d9433e239005f78bb99e25ecfe 100644 (file)
@@ -749,7 +749,6 @@ int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p,
        int i, r = 0;
 
        job->vm = NULL;
-       ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
 
        for (idx = 0; idx < ib->length_dw;) {
                uint32_t len = amdgpu_ib_get_value(ib, idx);
@@ -1044,7 +1043,6 @@ out:
        if (!r) {
                /* No error, free all destroyed handle slots */
                tmp = destroyed;
-               amdgpu_ib_free(p->adev, ib, NULL);
        } else {
                /* Error during parsing, free all allocated handle slots */
                tmp = allocated;
index 32517c364cf7a1367d8296edacbb02856b2ec427..4bfba2931b088ca3f5dae3165320ff111e65552e 100644 (file)
@@ -950,7 +950,7 @@ static const struct amdgpu_ring_funcs vce_v3_0_ring_vm_funcs = {
        .get_rptr = vce_v3_0_ring_get_rptr,
        .get_wptr = vce_v3_0_ring_get_wptr,
        .set_wptr = vce_v3_0_ring_set_wptr,
-       .parse_cs = amdgpu_vce_ring_parse_cs_vm,
+       .patch_cs_in_place = amdgpu_vce_ring_parse_cs_vm,
        .emit_frame_size =
                6 + /* vce_v3_0_emit_vm_flush */
                4 + /* vce_v3_0_emit_pipeline_sync */
index 06d787385ad460f9e78ff15b527d1b3a102d8eff..0748bf44c880868dde1eb6f92a68ef73d01b4b8f 100644 (file)
@@ -1102,7 +1102,7 @@ static const struct amdgpu_ring_funcs vce_v4_0_ring_vm_funcs = {
        .get_rptr = vce_v4_0_ring_get_rptr,
        .get_wptr = vce_v4_0_ring_get_wptr,
        .set_wptr = vce_v4_0_ring_set_wptr,
-       .parse_cs = amdgpu_vce_ring_parse_cs_vm,
+       .patch_cs_in_place = amdgpu_vce_ring_parse_cs_vm,
        .emit_frame_size =
                SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
                SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +