drm/xe/xe2: Add workaround 14019988906
authorTejas Upadhyay <tejas.upadhyay@intel.com>
Tue, 5 Dec 2023 05:21:59 +0000 (10:51 +0530)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 21 Dec 2023 16:45:24 +0000 (11:45 -0500)
This workaround applies to Graphics 20.04 as engine
workaround

V2(MattR):
 - Reorder bit define
 - Apply WA for RCS only

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/regs/xe_gt_regs.h
drivers/gpu/drm/xe/xe_wa.c

index d318ec0efd7dbe6ef32297e23599a8b63294fe0f..e8dc463a49f68fa7717aae6570df483964bf53e8 100644 (file)
 #define   SCOREBOARD_STALL_FLUSH_CONTROL       REG_BIT(5)
 
 #define XEHP_PSS_CHICKEN                       XE_REG_MCR(0x7044, XE_REG_OPTION_MASKED)
+#define   FLSH_IGNORES_PSD                     REG_BIT(10)
 #define   FD_END_COLLECT                       REG_BIT(5)
 
 #define HIZ_CHICKEN                                    XE_REG(0x7018, XE_REG_OPTION_MASKED)
index 63bd4bb1af039be60c91c3c7f9e32a61306fd6c3..ce897f2d49be24eb79d22c35828071b861926cc1 100644 (file)
@@ -719,6 +719,10 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
                       ENGINE_CLASS(RENDER)),
          XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
        },
+       { XE_RTP_NAME("14019988906"),
+         XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
+         XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
+       },
 
        {}
 };