net/mlx5e: Turn on HW tunnel offload in all TIRs
authorTariq Toukan <tariqt@mellanox.com>
Sun, 20 Jan 2019 09:04:34 +0000 (11:04 +0200)
committerSaeed Mahameed <saeedm@mellanox.com>
Wed, 1 May 2019 21:39:15 +0000 (14:39 -0700)
Hardware requires that all TIRs that steer traffic to the same RQ
should share identical tunneled_offload_en value.
For that, the tunneled_offload_en bit should be set/unset (according to
the HW capability) for all TIRs', not only the ones dedicated for
tunneled (inner) traffic.

Fixes: 1b223dd39162 ("net/mlx5e: Fix checksum handling for non-stripped vlan packets")
Signed-off-by: Tariq Toukan <tariqt@mellanox.com>
Signed-off-by: Saeed Mahameed <saeedm@mellanox.com>
drivers/net/ethernet/mellanox/mlx5/core/en.h
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
drivers/net/ethernet/mellanox/mlx5/core/en_rep.c
drivers/net/ethernet/mellanox/mlx5/core/ipoib/ipoib.c

index 7e0c3d4de108bcff8eb5252260f6ec45c7273a96..3a183d690e235e6457c6148eaf030627b5f6d2ed 100644 (file)
@@ -240,6 +240,7 @@ struct mlx5e_params {
        bool rx_cqe_compress_def;
        struct net_dim_cq_moder rx_cq_moderation;
        struct net_dim_cq_moder tx_cq_moderation;
+       bool tunneled_offload_en;
        bool lro_en;
        u8  tx_min_inline_mode;
        bool vlan_strip_disable;
index d713ab2e7a2d1ae1fa7feaa694086633ca0e1003..457cc39423f2ba26c6c40798904f5293e55d064f 100644 (file)
@@ -3100,6 +3100,8 @@ static void mlx5e_build_indir_tir_ctx_common(struct mlx5e_priv *priv,
        MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
        MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
        MLX5_SET(tirc, tirc, indirect_table, rqtn);
+       MLX5_SET(tirc, tirc, tunneled_offload_en,
+                priv->channels.params.tunneled_offload_en);
 
        mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
 }
@@ -3126,7 +3128,6 @@ static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
        mlx5e_build_indir_tir_ctx_common(priv, priv->indir_rqt.rqtn, tirc);
        mlx5e_build_indir_tir_ctx_hash(&priv->rss_params,
                                       &tirc_default_config[tt], tirc, true);
-       MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
 }
 
 int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv, bool inner_ttc)
@@ -4572,6 +4573,8 @@ void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
 
        /* RSS */
        mlx5e_build_rss_params(rss_params, params->num_channels);
+       params->tunneled_offload_en =
+               mlx5e_tunnel_inner_ft_supported(mdev);
 }
 
 static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
index 2ebca9bd5cf824d175bb29fe2373151fff7ea7e0..91e24f1cead885e73e5b1cfbd31fda7ebf809205 100644 (file)
@@ -1375,6 +1375,7 @@ static void mlx5e_build_rep_params(struct net_device *netdev)
        mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
 
        params->num_tc                = 1;
+       params->tunneled_offload_en = false;
 
        mlx5_query_min_inline(mdev, &params->tx_min_inline_mode);
 
index 9b03ae1e1e10d1f7e0516c9bebccd76258117dcd..ada1b7c0e0b8969a0a3397f89012c67aa8696bf2 100644 (file)
@@ -68,6 +68,7 @@ static void mlx5i_build_nic_params(struct mlx5_core_dev *mdev,
 
        params->lro_en = false;
        params->hard_mtu = MLX5_IB_GRH_BYTES + MLX5_IPOIB_HARD_LEN;
+       params->tunneled_offload_en = false;
 }
 
 /* Called directly after IPoIB netdevice was created to initialize SW structs */