arm64: dts: Add Adreno GPU definitions

Add an initial node for the Adreno GPU.

Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Andy Gross <agross@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index cbb7fe0fbbe5439cc03bc92e256940c71243ff08..d46858644c3dbc26e6da1cb1d5acca7e039aab6c 100644 (file)
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -84,6 +84,12 @@
                        qcom,client-id = <1>;
                        qcom,vmid = <15>;
                };
+
+               zap_shader_region: gpu@8f200000 {
+                       compatible = "shared-dma-pool";
+                       reg = <0x0 0x90b00000 0x0 0xa00000>;
+                       no-map;
+               };
        };
 
        cpus {
@@ -946,6 +952,11 @@
                                reg = <0x24f 0x1>;
                                bits = <1 4>;
                        };
+
+                       gpu_speed_bin: gpu_speed_bin@133 {
+                               reg = <0x133 0x1>;
+                               bits = <5 3>;
+                       };
                };
 
                phy@34000 {
@@ -1491,6 +1502,81 @@
                        };
                };
 
+               gpu@b00000 {
+                       compatible = "qcom,adreno-530.2", "qcom,adreno";
+                       #stream-id-cells = <16>;
+
+                       reg = <0xb00000 0x3f000>;
+                       reg-names = "kgsl_3d0_reg_memory";
+
+                       interrupts = <0 300 IRQ_TYPE_LEVEL_HIGH>;
+
+                       clocks = <&mmcc GPU_GX_GFX3D_CLK>,
+                               <&mmcc GPU_AHB_CLK>,
+                               <&mmcc GPU_GX_RBBMTIMER_CLK>,
+                               <&gcc GCC_BIMC_GFX_CLK>,
+                               <&gcc GCC_MMSS_BIMC_GFX_CLK>;
+
+                       clock-names = "core",
+                               "iface",
+                               "rbbmtimer",
+                               "mem",
+                               "mem_iface";
+
+                       power-domains = <&mmcc GPU_GDSC>;
+                       iommus = <&adreno_smmu 0>;
+
+                       nvmem-cells = <&gpu_speed_bin>;
+                       nvmem-cell-names = "speed_bin";
+
+                       qcom,gpu-quirk-two-pass-use-wfi;
+                       qcom,gpu-quirk-fault-detect-mask;
+
+                       operating-points-v2 = <&gpu_opp_table>;
+
+                       gpu_opp_table: opp-table {
+                               compatible  ="operating-points-v2";
+
+                               /*
+                                * 624Mhz and 560Mhz are only available on speed
+                                * bin (1 << 0). All the rest are available on
+                                * all bins of the hardware
+                                */
+                               opp-624000000 {
+                                       opp-hz = /bits/ 64 <624000000>;
+                                       opp-supported-hw = <0x01>;
+                               };
+                               opp-560000000 {
+                                       opp-hz = /bits/ 64 <560000000>;
+                                       opp-supported-hw = <0x01>;
+                               };
+                               opp-510000000 {
+                                       opp-hz = /bits/ 64 <510000000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                               opp-401800000 {
+                                       opp-hz = /bits/ 64 <401800000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                               opp-315000000 {
+                                       opp-hz = /bits/ 64 <315000000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                               opp-214000000 {
+                                       opp-hz = /bits/ 64 <214000000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                               opp-133000000 {
+                                       opp-hz = /bits/ 64 <133000000>;
+                                       opp-supported-hw = <0xFF>;
+                               };
+                       };
+
+                       zap-shader {
+                               memory-region = <&zap_shader_region>;
+                       };
+               };
+
                mdss: mdss@900000 {
                        compatible = "qcom,mdss";