ARM: dts: imx: Align L2 cache-controller nodename with dtschema

Fix dtschema validator warnings like:
    l2-cache@a02000: $nodename:0:
        'l2-cache@a02000' does not match '^(cache-controller|cpu)(@[0-9a-f,]+)*$'

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx35.dtsi b/arch/arm/boot/dts/imx35.dtsi
index e15408794d83d47465332f59536e923518f84c09..aba16252faab42d50fcd340989b328efd5223c34 100644 (file)
--- a/arch/arm/boot/dts/imx35.dtsi
+++ b/arch/arm/boot/dts/imx35.dtsi
@@ -59,7 +59,7 @@
                interrupt-parent = <&avic>;
                ranges;
 
-               L2: l2-cache@30000000 {
+               L2: cache-controller@30000000 {
                        compatible = "arm,l210-cache";
                        reg = <0x30000000 0x1000>;
                        cache-unified;

diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi
index 346a52fc96d9b5395cb125b6ce48a908baeaf0e8..3a0e222a1ab8bfd099eb9e163efb082d4d14aefa 100644 (file)
--- a/arch/arm/boot/dts/imx6qdl.dtsi
+++ b/arch/arm/boot/dts/imx6qdl.dtsi
@@ -245,7 +245,7 @@
                        interrupt-parent = <&intc>;
                };
 
-               L2: l2-cache@a02000 {
+               L2: cache-controller@a02000 {
                        compatible = "arm,pl310-cache";
                        reg = <0x00a02000 0x1000>;
                        interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;

diff --git a/arch/arm/boot/dts/imx6sl.dtsi b/arch/arm/boot/dts/imx6sl.dtsi
index e2d25328b57919e21cb262b19e24eb0add3cb21c..eb8aeaa5ccab6e186c76a5b4dd8c53b51c26d885 100644 (file)
--- a/arch/arm/boot/dts/imx6sl.dtsi
+++ b/arch/arm/boot/dts/imx6sl.dtsi
@@ -126,7 +126,7 @@
                        interrupt-parent = <&intc>;
                };
 
-               L2: l2-cache@a02000 {
+               L2: cache-controller@a02000 {
                        compatible = "arm,pl310-cache";
                        reg = <0x00a02000 0x1000>;
                        interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>;

diff --git a/arch/arm/boot/dts/imx6sll.dtsi b/arch/arm/boot/dts/imx6sll.dtsi
index 3d1a689f5dec9b5f7edf7c10ef42b337bdbee667..554a31ea9c0751304ad79f925d285152f9ffa186 100644 (file)
--- a/arch/arm/boot/dts/imx6sll.dtsi
+++ b/arch/arm/boot/dts/imx6sll.dtsi
@@ -126,7 +126,7 @@
                        interrupt-parent = <&intc>;
                };
 
-               L2: l2-cache@a02000 {
+               L2: cache-controller@a02000 {
                        compatible = "arm,pl310-cache";
                        reg = <0x00a02000 0x1000>;
                        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;

diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi
index fcb3d064d0ccc53f62ffb0ca3de1b0fc35665422..939fda91d4473ff0861bf462883450ed74492acf 100644 (file)
--- a/arch/arm/boot/dts/imx6sx.dtsi
+++ b/arch/arm/boot/dts/imx6sx.dtsi
@@ -179,7 +179,7 @@
                        interrupt-parent = <&intc>;
                };
 
-               L2: l2-cache@a02000 {
+               L2: cache-controller@a02000 {
                        compatible = "arm,pl310-cache";
                        reg = <0x00a02000 0x1000>;
                        interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;