drm/amdgpu: use AMDGPU_NUM_VMID when possible

Replace hardcoded vmid number with AMDGPU_NUM_VMID macro.

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 157ae3004cc2d2f556c378edc0acf58b23422a63..ba108678452551f0917d01ff67cf6c186822a171 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4844,7 +4844,7 @@ static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
         * the driver can enable them for graphics. VMID0 should maintain
         * access so that HWS firmware can save/restore entries.
         */
-       for (vmid = 1; vmid < 16; vmid++) {
+       for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index f2490f915a8be91b276b058e959b2086d9d3a967..a368724c3dfcd079bd89e72639ba260d69226ce0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1896,7 +1896,7 @@ static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev)
         * the driver can enable them for graphics. VMID0 should maintain
         * access so that HWS firmware can save/restore entries.
         */
-       for (vmid = 1; vmid < 16; vmid++) {
+       for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
                WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
                WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
                WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 9a905531f83772b72fd23896a041bd4a34431c5a..37639214cbbbd5edeca3e97a93360c4e4ab32020 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3749,7 +3749,7 @@ static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
         * the driver can enable them for graphics. VMID0 should maintain
         * access so that HWS firmware can save/restore entries.
         */
-       for (vmid = 1; vmid < 16; vmid++) {
+       for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
                WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
                WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
                WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 60519431ed9176de58bd361fa3bb6533f5f1e1b3..fc9bb94eaaf421bdf5c99db12ab79231eb0c51c3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2520,7 +2520,7 @@ static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
         * the driver can enable them for graphics. VMID0 should maintain
         * access so that HWS firmware can save/restore entries.
         */
-       for (vmid = 1; vmid < 16; vmid++) {
+       for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
                WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
index 5317efc942a43c40b98075a75142d17cd367d184..11fedcf86fae61984f5746748e16c715abb0a9b2 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
@@ -432,7 +432,7 @@ static int gmc_v10_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
                return 0;
        }
 
-       for (vmid = 1; vmid < 16; vmid++) {
+       for (vmid = 1; vmid < AMDGPU_NUM_VMID; vmid++) {
 
                ret = gmc_v10_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
                                &queried_pasid);

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index 95a9117e95640e5a31cb569d678cff8f1716e4a6..998d6c8fde7922e2f8265c4aa255235fb2a9f1ae 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -530,7 +530,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
         * the VMs are determined by the application and setup and assigned
         * on the fly in the vm part of radeon_gart.c
         */
-       for (i = 1; i < 16; i++) {
+       for (i = 1; i < AMDGPU_NUM_VMID; i++) {
                if (i < 8)
                        WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
                               table_addr >> 12);

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index d9cb887b3a9147dcabff3b0e75958d1f2ea27c5d..d06e3f5e38ae64e26aa5d429d38628d48ba07465 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -677,7 +677,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
        /* set vm size, must be a multiple of 4 */
        WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
        WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
-       for (i = 1; i < 16; i++) {
+       for (i = 1; i < AMDGPU_NUM_VMID; i++) {
                if (i < 8)
                        WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
                               table_addr >> 12);

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 65d7bc1081518622c5bf87522c9e6966e80bc31b..e8d07109c6282988064fb8ef3b6f0bf5adebe2ac 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -903,7 +903,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
        /* set vm size, must be a multiple of 4 */
        WREG32(mmVM_CONTEXT1_PAGE_TABLE_START_ADDR, 0);
        WREG32(mmVM_CONTEXT1_PAGE_TABLE_END_ADDR, adev->vm_manager.max_pfn - 1);
-       for (i = 1; i < 16; i++) {
+       for (i = 1; i < AMDGPU_NUM_VMID; i++) {
                if (i < 8)
                        WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
                               table_addr >> 12);

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 0309d84c887d06d6167c9f80b8350c5a728e4485..d7b39c07de2054c38d56830f9207c87e790c0f3b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -344,7 +344,7 @@ static void mmhub_v1_0_gart_disable(struct amdgpu_device *adev)
        u32 i;
 
        /* Disable all tables */
-       for (i = 0; i < 16; i++)
+       for (i = 0; i < AMDGPU_NUM_VMID; i++)
                WREG32_SOC15_OFFSET(MMHUB, 0, mmVM_CONTEXT0_CNTL,
                                    i * hub->ctx_distance, 0);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
index 57d5f8ffb764cc9257c44f7008c0522bb16df035..092ff2c436580a0cb1418cefa362fd84b8e6ce5d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c
@@ -421,7 +421,7 @@ static void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
        u32 i;
 
        /* Disable all tables */
-       for (i = 0; i < 16; i++)
+       for (i = 0; i < AMDGPU_NUM_VMID; i++)
                WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
                                    i * hub->ctx_distance, 0);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
index fa77eae6cf47ef7f28852b2cda98c93e51a9a9b4..b72c8e4ca36bdf3940aab63c1b1f8965fc774523 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.c
@@ -376,7 +376,7 @@ static void mmhub_v2_3_gart_disable(struct amdgpu_device *adev)
        u32 i;
 
        /* Disable all tables */
-       for (i = 0; i < 16; i++)
+       for (i = 0; i < AMDGPU_NUM_VMID; i++)
                WREG32_SOC15_OFFSET(MMHUB, 0, mmMMVM_CONTEXT0_CNTL,
                                    i * hub->ctx_distance, 0);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
index 66748bb01b525c6abae47e81d085d4e3c0f4526b..4a31737b6bb0b488180b496b207f4b4f45c3eda7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c
@@ -405,7 +405,7 @@ static void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
 
        for (j = 0; j < MMHUB_NUM_INSTANCES; j++) {
                /* Disable all tables */
-               for (i = 0; i < 16; i++)
+               for (i = 0; i < AMDGPU_NUM_VMID; i++)
                        WREG32_SOC15_OFFSET(MMHUB, 0,
                                            mmVML2VC0_VM_CONTEXT0_CNTL,
                                            j * MMHUB_INSTANCE_REGISTER_OFFSET +