drm/amd/display: Ensure array index tg_inst won't be -1

[WHY & HOW]
tg_inst will be a negative if timing_generator_count equals 0, which
should be checked before used.

This fixes 2 OVERRUN issues reported by Coverity.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Acked-by: Tom Chung <chiahsuan.chung@amd.com>
Signed-off-by: Alex Hung <alex.hung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 8dcd7eac4b2b16dd31ce5e5f89dcaa622353b397..dbcd34c6338b63299f0670bd055fc57050fd2cce 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -3542,7 +3542,7 @@ static bool acquire_otg_master_pipe_for_stream(
                if (pool->dpps[pipe_idx])
                        pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
 
-               if (pipe_idx >= pool->timing_generator_count) {
+               if (pipe_idx >= pool->timing_generator_count && pool->timing_generator_count != 0) {
                        int tg_inst = pool->timing_generator_count - 1;
 
                        pipe_ctx->stream_res.tg = pool->timing_generators[tg_inst];