dt-bindings: clk: cleanup comments
authorTom Rix <trix@redhat.com>
Wed, 9 Mar 2022 22:23:02 +0000 (14:23 -0800)
committerRob Herring <robh@kernel.org>
Thu, 10 Mar 2022 23:22:25 +0000 (17:22 -0600)
For spdx, first line /* */ for *.h, change tab to space

Replacements
devider to divider
Comunications to Communications
periphrals to peripherals
supportted to supported
wich to which
Documentatoin to Documentation

Signed-off-by: Tom Rix <trix@redhat.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220309222302.1114561-1-trix@redhat.com
include/dt-bindings/clock/alphascale,asm9260.h
include/dt-bindings/clock/axis,artpec6-clkctrl.h
include/dt-bindings/clock/boston-clock.h
include/dt-bindings/clock/marvell,mmp2.h
include/dt-bindings/clock/marvell,pxa168.h
include/dt-bindings/clock/marvell,pxa910.h
include/dt-bindings/clock/nuvoton,npcm7xx-clock.h
include/dt-bindings/clock/stm32fx-clock.h
include/dt-bindings/clock/stratix10-clock.h

index d3871c63308be302940b2dc2124136738b962821..f53f8b16883d680710fddf259cf0ba0bea60e55f 100644 (file)
@@ -55,7 +55,7 @@
 #define CLKID_AHB_I2S1         45
 #define CLKID_AHB_MAC1         46
 
-/* devider */
+/* divider */
 #define CLKID_SYS_CPU          47
 #define CLKID_SYS_AHB          48
 #define CLKID_SYS_I2S0M                49
index b1f4971642e6f2d63b5a3032458075739ca78bf5..14e424a7c08c2da5fb5bc78676940498469f078a 100644 (file)
@@ -2,7 +2,7 @@
 /*
  * ARTPEC-6 clock controller indexes
  *
- * Copyright 2016 Axis Comunications AB.
+ * Copyright 2016 Axis Communications AB.
  */
 
 #ifndef DT_BINDINGS_CLK_ARTPEC6_CLKCTRL_H
index a6f0098211378654cc8321860b88da4ba972a850..38140fa87b09d00e1539ddb36e57a9c3a20c9466 100644 (file)
@@ -1,7 +1,6 @@
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (C) 2016 Imagination Technologies
- *
- * SPDX-License-Identifier:    GPL-2.0
  */
 
 #ifndef __DT_BINDINGS_CLOCK_BOSTON_CLOCK_H__
index 87f5ad5df72f4041dd385f8ff17918f3234efc1f..f0819d66b2306608e5c732b9ef2b64a22fb4a2ac 100644 (file)
@@ -32,7 +32,7 @@
 #define MMP2_CLK_I2S0                  31
 #define MMP2_CLK_I2S1                  32
 
-/* apb periphrals */
+/* apb peripherals */
 #define MMP2_CLK_TWSI0                 60
 #define MMP2_CLK_TWSI1                 61
 #define MMP2_CLK_TWSI2                 62
@@ -60,7 +60,7 @@
 #define MMP3_CLK_THERMAL2              84
 #define MMP3_CLK_THERMAL3              85
 
-/* axi periphrals */
+/* axi peripherals */
 #define MMP2_CLK_SDH0                  101
 #define MMP2_CLK_SDH1                  102
 #define MMP2_CLK_SDH2                  103
index caf90436b84836ad4bb62f6591c7ea5e479169f5..db2b41f1b127257bb3439a7fde566e4ce2f9a544 100644 (file)
@@ -23,7 +23,7 @@
 #define PXA168_CLK_UART_PLL            27
 #define PXA168_CLK_USB_PLL             28
 
-/* apb periphrals */
+/* apb peripherals */
 #define PXA168_CLK_TWSI0               60
 #define PXA168_CLK_TWSI1               61
 #define PXA168_CLK_TWSI2               62
@@ -45,7 +45,7 @@
 #define PXA168_CLK_SSP4                        78
 #define PXA168_CLK_TIMER               79
 
-/* axi periphrals */
+/* axi peripherals */
 #define PXA168_CLK_DFC                 100
 #define PXA168_CLK_SDH0                        101
 #define PXA168_CLK_SDH1                        102
index 7bf46238946eb2edb290a32c79ba02f09f62d1ed..c9018ab354d060b8d4c6e6255876cba40239802d 100644 (file)
@@ -23,7 +23,7 @@
 #define PXA910_CLK_UART_PLL            27
 #define PXA910_CLK_USB_PLL             28
 
-/* apb periphrals */
+/* apb peripherals */
 #define PXA910_CLK_TWSI0               60
 #define PXA910_CLK_TWSI1               61
 #define PXA910_CLK_TWSI2               62
@@ -43,7 +43,7 @@
 #define PXA910_CLK_TIMER0              76
 #define PXA910_CLK_TIMER1              77
 
-/* axi periphrals */
+/* axi peripherals */
 #define PXA910_CLK_DFC                 100
 #define PXA910_CLK_SDH0                        101
 #define PXA910_CLK_SDH1                        102
index f21522605b94b74b57ac7fabece973752c568f81..3e0a9b68933dfe2105201f13f218a79fb9a523f1 100644 (file)
@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Nuvoton NPCM7xx Clock Generator binding
- * clock binding number for all clocks supportted by nuvoton,npcm7xx-clk
+ * clock binding number for all clocks supported by nuvoton,npcm7xx-clk
  *
  * Copyright (C) 2018 Nuvoton Technologies tali.perry@nuvoton.com
  *
index 1cc89c548578bbc404c987cf226de40f5f5a9deb..e5dad050d518a9615fcb534ec58d210384ffe3f8 100644 (file)
@@ -7,10 +7,10 @@
  */
 
 /*
- * List of clocks wich are not derived from system clock (SYSCLOCK)
+ * List of clocks which are not derived from system clock (SYSCLOCK)
  *
  * The index of these clocks is the secondary index of DT bindings
- * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
+ * (see Documentation/devicetree/bindings/clock/st,stm32-rcc.txt)
  *
  * e.g:
        <assigned-clocks = <&rcc 1 CLK_LSE>;
index 08b98e20b7cc74a87c1e6289d112d8bb25ae5a46..636498f9e08ee524915f4e58909a841baa9211be 100644 (file)
@@ -1,4 +1,4 @@
-/* SPDX-License-Identifier:    GPL-2.0 */
+/* SPDX-License-Identifier: GPL-2.0 */
 /*
  * Copyright (C) 2017, Intel Corporation
  */