ARM: dts: am335x: boneblack-wireless: Replaced register offsets with defines

The defines are taken from dt-bindings/pinctrl/am33xx.h

Signed-off-by: Christina Quast <cquast@hanoverdisplays.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/am335x-boneblack-wireless.dts b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
index 83f49f616b19c021da9b65ad7db2ec9415f5da2b..5b275c96fccf5d955cfaf5f845f3fdaeb9e4b274 100644 (file)
--- a/arch/arm/boot/dts/am335x-boneblack-wireless.dts
+++ b/arch/arm/boot/dts/am335x-boneblack-wireless.dts
@@ -32,35 +32,35 @@
 &am33xx_pinmux {
        bt_pins: pinmux_bt_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x928, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gmii1_txd0.gpio0_28 - BT_EN */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLUP, MUX_MODE7)      /* gmii1_txd0.gpio0_28 - BT_EN */
                >;
        };
 
        mmc3_pins: pinmux_mmc3_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x93c, PIN_INPUT_PULLUP | MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */
-                       AM33XX_IOPAD(0x914, PIN_INPUT_PULLUP | MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */
-                       AM33XX_IOPAD(0x918, PIN_INPUT_PULLUP | MUX_MODE5 ) /* (J17) gmii1_rxdv.mmc2_dat0 */
-                       AM33XX_IOPAD(0x91c, PIN_INPUT_PULLUP | MUX_MODE5 ) /* (J18) gmii1_txd3.mmc2_dat1 */
-                       AM33XX_IOPAD(0x920, PIN_INPUT_PULLUP | MUX_MODE5 ) /* (K15) gmii1_txd2.mmc2_dat2 */
-                       AM33XX_IOPAD(0x908, PIN_INPUT_PULLUP | MUX_MODE5 ) /* (H16) gmii1_col.mmc2_dat3 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (L15) gmii1_rxd1.mmc2_clk */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLUP, MUX_MODE6 ) /* (J16) gmii1_txen.mmc2_cmd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J17) gmii1_rxdv.mmc2_dat0 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (J18) gmii1_txd3.mmc2_dat1 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (K15) gmii1_txd2.mmc2_dat2 */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_COL, PIN_INPUT_PULLUP, MUX_MODE5 ) /* (H16) gmii1_col.mmc2_dat3 */
                >;
        };
 
        uart3_pins: pinmux_uart3_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1)       /* gmii1_rxd3.uart3_rxd */
-                       AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLDOWN | MUX_MODE1)    /* gmii1_rxd2.uart3_txd */
-                       AM33XX_IOPAD(0x948, PIN_INPUT | MUX_MODE3)              /* mdio_data.uart3_ctsn */
-                       AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLDOWN | MUX_MODE3)    /* mdio_clk.uart3_rtsn */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLUP, MUX_MODE1)       /* gmii1_rxd3.uart3_rxd */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE1)    /* gmii1_rxd2.uart3_txd */
+                       AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT, MUX_MODE3)           /* mdio_data.uart3_ctsn */
+                       AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLDOWN, MUX_MODE3)  /* mdio_clk.uart3_rtsn */
                >;
        };
 
        wl18xx_pins: pinmux_wl18xx_pins {
                pinctrl-single,pins = <
-                       AM33XX_IOPAD(0x92c, PIN_OUTPUT_PULLDOWN | MUX_MODE7)    /* gmii1_txclk.gpio3_9 WL_EN */
-                       AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7)     /* rmii1_refclk.gpio0_29 WL_IRQ */
-                       AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLUP | MUX_MODE7)      /* gmii1_rxclk.gpio3_10 LS_BUF_EN */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE7)  /* gmii1_txclk.gpio3_9 WL_EN */
+                       AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7) /* rmii1_refclk.gpio0_29 WL_IRQ */
+                       AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7)    /* gmii1_rxclk.gpio3_10 LS_BUF_EN */
                >;
        };
 };