riscv: dts: sophgo: add initial CV1812H SoC device tree

Add initial device tree for the CV1812H RISC-V SoC by SOPHGO.

Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Acked-by: Chen Wang <unicorn_wang@outlook.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/sophgo/cv1812h.dtsi b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
new file mode 100644 (file)
index 0000000..3e7a942
--- /dev/null
+++ b/arch/riscv/boot/dts/sophgo/cv1812h.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2023 Inochi Amaoto <inochiama@outlook.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include "cv18xx.dtsi"
+
+/ {
+       compatible = "sophgo,cv1812h";
+
+       memory@80000000 {
+               device_type = "memory";
+               reg = <0x80000000 0x10000000>;
+       };
+};
+
+&plic {
+       compatible = "sophgo,cv1812h-plic", "thead,c900-plic";
+};
+
+&clint {
+       compatible = "sophgo,cv1812h-clint", "thead,c900-clint";
+};