drm/amdgpu: Add replay counter defines to NBIO headers

Add the PCIE_RX_NUM_NACK and PCIE_RX_NUM_NACK_GENERATED values to the
NBIO SMN headers in preparation for exposing the number of PCIe replays
via sysfs

Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
index 8c75669eb5008272f444f39ce2ae870f6d431963..9470ec5e0f426257b02de59e1d1fd479bfac85ae 100644 (file)
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_1_smn.h
@@ -54,5 +54,8 @@
 #define smnPCIE_PERF_COUNT0_TXCLK2                     0x11180258
 #define smnPCIE_PERF_COUNT1_TXCLK2                     0x1118025c
 
+#define smnPCIE_RX_NUM_NAK                             0x11180038
+#define smnPCIE_RX_NUM_NAK_GENERATED                   0x1118003c
+
 #endif // _nbio_6_1_SMN_HEADER
 

diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
index 5563f071589625371767fbfa9cbdcb93d9621dbd..caf5ffdc130aa2d134b6357c8f4da0094f321bd9 100644 (file)
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_0_smn.h
@@ -51,4 +51,7 @@
 #define smnPCIE_PERF_COUNT0_TXCLK2                     0x11180258
 #define smnPCIE_PERF_COUNT1_TXCLK2                     0x1118025c
 
+#define smnPCIE_RX_NUM_NAK                             0x11180038
+#define smnPCIE_RX_NUM_NAK_GENERATED                   0x1118003c
+
 #endif // _nbio_7_0_SMN_HEADER

diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
index c1457d880c4d6d349fc36f2a749e5b19662715ef..4bcacf5298528c5139ba789ff646d40c3959fe2c 100644 (file)
--- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_0_smn.h
@@ -50,4 +50,7 @@
 #define smnPCIE_PERF_CNTL_EVENT_LC_PORT_SEL            0x1118024c
 #define smnPCIE_PERF_CNTL_EVENT_CI_PORT_SEL            0x11180250
 
+#define smnPCIE_RX_NUM_NAK                             0x11180038
+#define smnPCIE_RX_NUM_NAK_GENERATED                   0x1118003c
+
 #endif // _nbio_7_4_0_SMN_HEADER