drm/i915: Move pipe/transcoder/abox masks under intel_device_info.display

Collect the dipslay related mask under the display sub-structure
in intel_device_info.

Note that there is a slight change in behaviour in that we zero
out .display entirely when !HAS_DISPLAY (aka. pipe_mask==0), so
now we also zero out the other masks (although cpu_transocder_mask
should already be zero of pipe_mask is zero). abox_mask is
only used by the display core init when HAS_DISPLAY is true, so
the actual behaviour of the system shouldn't change despite the
zeroing of these masks.

There is a lot more display stuff directly in device info that
could be moved over. Maybe someone else will be inspired to do it...

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211210122726.12577-1-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 4b688a9727b39af609a3dfe3d03e01dbc89ea436..43fd2f0a3e5e03e2c8d37804b21d65cc985bd3d0 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -372,7 +372,7 @@ enum hpd_pin {
 
 #define for_each_pipe(__dev_priv, __p) \
        for ((__p) = 0; (__p) < I915_MAX_PIPES; (__p)++) \
-               for_each_if(INTEL_INFO(__dev_priv)->pipe_mask & BIT(__p))
+               for_each_if(INTEL_INFO(__dev_priv)->display.pipe_mask & BIT(__p))
 
 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
        for_each_pipe(__dev_priv, __p) \
@@ -380,7 +380,7 @@ enum hpd_pin {
 
 #define for_each_cpu_transcoder(__dev_priv, __t) \
        for ((__t) = 0; (__t) < I915_MAX_TRANSCODERS; (__t)++)  \
-               for_each_if (INTEL_INFO(__dev_priv)->cpu_transcoder_mask & BIT(__t))
+               for_each_if (INTEL_INFO(__dev_priv)->display.cpu_transcoder_mask & BIT(__t))
 
 #define for_each_cpu_transcoder_masked(__dev_priv, __t, __mask) \
        for_each_cpu_transcoder(__dev_priv, __t) \

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 229b4c127c6cedf3a10deb0933235c149cb0d9f1..05babdcf5f2e9688ae2748be49748bf25df84ebd 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -5370,7 +5370,7 @@ static void gen12_dbuf_slices_config(struct drm_i915_private *dev_priv)
 
 static void icl_mbus_init(struct drm_i915_private *dev_priv)
 {
-       unsigned long abox_regs = INTEL_INFO(dev_priv)->abox_mask;
+       unsigned long abox_regs = INTEL_INFO(dev_priv)->display.abox_mask;
        u32 mask, val, i;
 
        if (IS_ALDERLAKE_P(dev_priv))
@@ -5830,7 +5830,7 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
        enum intel_dram_type type = dev_priv->dram_info.type;
        u8 num_channels = dev_priv->dram_info.num_channels;
        const struct buddy_page_mask *table;
-       unsigned long abox_mask = INTEL_INFO(dev_priv)->abox_mask;
+       unsigned long abox_mask = INTEL_INFO(dev_priv)->display.abox_mask;
        int config, i;
 
        /* BW_BUDDY registers are not used on dgpu's beyond DG1 */

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d8e4e1115ef8b95c7901b3e1cea9789416d0d81c..e99996dfd43a121d8ba7e3758d18f27f3286ed8b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1506,7 +1506,7 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define HAS_PSR_HW_TRACKING(dev_priv) \
        (INTEL_INFO(dev_priv)->display.has_psr_hw_tracking)
 #define HAS_PSR2_SEL_FETCH(dev_priv)    (GRAPHICS_VER(dev_priv) >= 12)
-#define HAS_TRANSCODER(dev_priv, trans)         ((INTEL_INFO(dev_priv)->cpu_transcoder_mask & BIT(trans)) != 0)
+#define HAS_TRANSCODER(dev_priv, trans)         ((INTEL_INFO(dev_priv)->display.cpu_transcoder_mask & BIT(trans)) != 0)
 
 #define HAS_RC6(dev_priv)               (INTEL_INFO(dev_priv)->has_rc6)
 #define HAS_RC6p(dev_priv)              (INTEL_INFO(dev_priv)->has_rc6p)
@@ -1551,9 +1551,9 @@ IS_SUBPLATFORM(const struct drm_i915_private *i915,
 #define GT_FREQUENCY_MULTIPLIER 50
 #define GEN9_FREQ_SCALER 3
 
-#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->pipe_mask))
+#define INTEL_NUM_PIPES(dev_priv) (hweight8(INTEL_INFO(dev_priv)->display.pipe_mask))
 
-#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->pipe_mask != 0)
+#define HAS_DISPLAY(dev_priv) (INTEL_INFO(dev_priv)->display.pipe_mask != 0)
 
 #define HAS_VRR(i915)  (GRAPHICS_VER(i915) >= 11)
 

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 158d160e39964494b4cb7cb337ce5fff7b3cc128..eeee028a5ad72789c86195d84182d170918a436e 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -162,8 +162,8 @@
 #define I830_FEATURES \
        GEN(2), \
        .is_mobile = 1, \
-       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
-       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
+       .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
        .display.has_overlay = 1, \
        .display.cursor_needs_physical = 1, \
        .display.overlay_needs_physical = 1, \
@@ -183,8 +183,8 @@
 
 #define I845_FEATURES \
        GEN(2), \
-       .pipe_mask = BIT(PIPE_A), \
-       .cpu_transcoder_mask = BIT(TRANSCODER_A), \
+       .display.pipe_mask = BIT(PIPE_A), \
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A), \
        .display.has_overlay = 1, \
        .display.overlay_needs_physical = 1, \
        .display.has_gmch = 1, \
@@ -225,8 +225,8 @@ static const struct intel_device_info i865g_info = {
 
 #define GEN3_FEATURES \
        GEN(3), \
-       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
-       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
+       .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
        .display.has_gmch = 1, \
        .gpu_reset_clobbers_display = true, \
        .platform_engine_mask = BIT(RCS0), \
@@ -315,8 +315,8 @@ static const struct intel_device_info pnv_m_info = {
 
 #define GEN4_FEATURES \
        GEN(4), \
-       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
-       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
+       .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
        .display.has_hotplug = 1, \
        .display.has_gmch = 1, \
        .gpu_reset_clobbers_display = true, \
@@ -368,8 +368,8 @@ static const struct intel_device_info gm45_info = {
 
 #define GEN5_FEATURES \
        GEN(5), \
-       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
-       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
+       .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
        .display.has_hotplug = 1, \
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0), \
        .has_snoop = true, \
@@ -398,8 +398,8 @@ static const struct intel_device_info ilk_m_info = {
 
 #define GEN6_FEATURES \
        GEN(6), \
-       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
-       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
+       .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B), \
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B), \
        .display.has_hotplug = 1, \
        .display.has_fbc = 1, \
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
@@ -449,8 +449,8 @@ static const struct intel_device_info snb_m_gt2_info = {
 
 #define GEN7_FEATURES  \
        GEN(7), \
-       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
-       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
+       .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C), \
        .display.has_hotplug = 1, \
        .display.has_fbc = 1, \
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0), \
@@ -504,8 +504,8 @@ static const struct intel_device_info ivb_q_info = {
        GEN7_FEATURES,
        PLATFORM(INTEL_IVYBRIDGE),
        .gt = 2,
-       .pipe_mask = 0, /* legal, last one wins */
-       .cpu_transcoder_mask = 0,
+       .display.pipe_mask = 0, /* legal, last one wins */
+       .display.cpu_transcoder_mask = 0,
        .has_l3_dpf = 1,
 };
 
@@ -513,8 +513,8 @@ static const struct intel_device_info vlv_info = {
        PLATFORM(INTEL_VALLEYVIEW),
        GEN(7),
        .is_lp = 1,
-       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
-       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
+       .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B),
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B),
        .has_runtime_pm = 1,
        .has_rc6 = 1,
        .has_reset_engine = true,
@@ -538,7 +538,7 @@ static const struct intel_device_info vlv_info = {
 #define G75_FEATURES  \
        GEN7_FEATURES, \
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
-       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
                BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP), \
        .display.has_ddi = 1, \
        .display.has_fpga_dbg = 1, \
@@ -608,8 +608,8 @@ static const struct intel_device_info bdw_gt3_info = {
 static const struct intel_device_info chv_info = {
        PLATFORM(INTEL_CHERRYVIEW),
        GEN(8),
-       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
-       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
+       .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | BIT(TRANSCODER_C),
        .display.has_hotplug = 1,
        .is_lp = 1,
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0),
@@ -686,8 +686,8 @@ static const struct intel_device_info skl_gt4_info = {
        .dbuf.slice_mask = BIT(DBUF_S1), \
        .display.has_hotplug = 1, \
        .platform_engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
-       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
-       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+       .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
                BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
                BIT(TRANSCODER_DSI_A) | BIT(TRANSCODER_DSI_C), \
        .has_64bit_reloc = 1, \
@@ -795,8 +795,8 @@ static const struct intel_device_info cml_gt2_info = {
 #define GEN11_FEATURES \
        GEN9_FEATURES, \
        GEN11_DEFAULT_PAGE_SIZES, \
-       .abox_mask = BIT(0), \
-       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+       .display.abox_mask = BIT(0), \
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
                BIT(TRANSCODER_C) | BIT(TRANSCODER_EDP) | \
                BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
        .pipe_offsets = { \
@@ -847,9 +847,9 @@ static const struct intel_device_info jsl_info = {
 #define GEN12_FEATURES \
        GEN11_FEATURES, \
        GEN(12), \
-       .abox_mask = GENMASK(2, 1), \
-       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
-       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
+       .display.abox_mask = GENMASK(2, 1), \
+       .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D), \
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | \
                BIT(TRANSCODER_C) | BIT(TRANSCODER_D) | \
                BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1), \
        .pipe_offsets = { \
@@ -884,9 +884,9 @@ static const struct intel_device_info tgl_info = {
 static const struct intel_device_info rkl_info = {
        GEN12_FEATURES,
        PLATFORM(INTEL_ROCKETLAKE),
-       .abox_mask = BIT(0),
-       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
-       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+       .display.abox_mask = BIT(0),
+       .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
                BIT(TRANSCODER_C),
        .display.has_hti = 1,
        .display.has_psr_hw_tracking = 0,
@@ -906,7 +906,7 @@ static const struct intel_device_info dg1_info = {
        DGFX_FEATURES,
        .graphics_rel = 10,
        PLATFORM(INTEL_DG1),
-       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+       .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
        .require_force_probe = 1,
        .platform_engine_mask =
                BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
@@ -918,7 +918,7 @@ static const struct intel_device_info dg1_info = {
 static const struct intel_device_info adl_s_info = {
        GEN12_FEATURES,
        PLATFORM(INTEL_ALDERLAKE_S),
-       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+       .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
        .display.has_hti = 1,
        .display.has_psr_hw_tracking = 0,
        .platform_engine_mask =
@@ -935,7 +935,7 @@ static const struct intel_device_info adl_s_info = {
        }
 
 #define XE_LPD_FEATURES \
-       .abox_mask = GENMASK(1, 0),                                             \
+       .display.abox_mask = GENMASK(1, 0),                                     \
        .color = { .degamma_lut_size = 128, .gamma_lut_size = 1024,             \
                   .degamma_lut_tests = DRM_COLOR_LUT_NON_DECREASING |          \
                                        DRM_COLOR_LUT_EQUAL_CHANNELS,           \
@@ -955,7 +955,7 @@ static const struct intel_device_info adl_s_info = {
        .display.has_ipc = 1,                                                   \
        .display.has_psr = 1,                                                   \
        .display.ver = 13,                                                      \
-       .pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),     \
+       .display.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),     \
        .pipe_offsets = {                                                       \
                [TRANSCODER_A] = PIPE_A_OFFSET,                                 \
                [TRANSCODER_B] = PIPE_B_OFFSET,                                 \
@@ -978,7 +978,7 @@ static const struct intel_device_info adl_p_info = {
        GEN12_FEATURES,
        XE_LPD_FEATURES,
        PLATFORM(INTEL_ALDERLAKE_P),
-       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
                               BIT(TRANSCODER_C) | BIT(TRANSCODER_D) |
                               BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1),
        .display.has_cdclk_crawl = 1,
@@ -1027,7 +1027,6 @@ static const struct intel_device_info xehpsdv_info = {
        DGFX_FEATURES,
        PLATFORM(INTEL_XEHPSDV),
        .display = { },
-       .pipe_mask = 0,
        .platform_engine_mask =
                BIT(RCS0) | BIT(BCS0) |
                BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
@@ -1050,7 +1049,7 @@ static const struct intel_device_info dg2_info = {
                BIT(VECS0) | BIT(VECS1) |
                BIT(VCS0) | BIT(VCS2),
        .require_force_probe = 1,
-       .cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+       .display.cpu_transcoder_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
                               BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
 };
 

diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 6b2d577d74ed4cbef6b7ab02c720675664152d74..cbe9972478ac67766d7c336850500be0bc1b580f 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -333,33 +333,33 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
                     !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
                        drm_info(&dev_priv->drm,
                                 "Display fused off, disabling\n");
-                       info->pipe_mask = 0;
-                       info->cpu_transcoder_mask = 0;
+                       info->display.pipe_mask = 0;
+                       info->display.cpu_transcoder_mask = 0;
                } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
                        drm_info(&dev_priv->drm, "PipeC fused off\n");
-                       info->pipe_mask &= ~BIT(PIPE_C);
-                       info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
+                       info->display.pipe_mask &= ~BIT(PIPE_C);
+                       info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
                }
        } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
                u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
 
                if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
-                       info->pipe_mask &= ~BIT(PIPE_A);
-                       info->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
+                       info->display.pipe_mask &= ~BIT(PIPE_A);
+                       info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
                }
                if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
-                       info->pipe_mask &= ~BIT(PIPE_B);
-                       info->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
+                       info->display.pipe_mask &= ~BIT(PIPE_B);
+                       info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
                }
                if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
-                       info->pipe_mask &= ~BIT(PIPE_C);
-                       info->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
+                       info->display.pipe_mask &= ~BIT(PIPE_C);
+                       info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
                }
 
                if (DISPLAY_VER(dev_priv) >= 12 &&
                    (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
-                       info->pipe_mask &= ~BIT(PIPE_D);
-                       info->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
+                       info->display.pipe_mask &= ~BIT(PIPE_D);
+                       info->display.cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
                }
 
                if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)

diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index ac427d6ae305accb656833f39c62d9489afcf33b..c121d7309dd23a8089ea4fae9e73fb7d2dd27d71 100644 (file)
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -192,11 +192,6 @@ struct intel_device_info {
 
        u8 gt; /* GT number, 0 if undefined */
 
-       u8 pipe_mask;
-       u8 cpu_transcoder_mask;
-
-       u8 abox_mask;
-
 #define DEFINE_FLAG(name) u8 name:1
        DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG);
 #undef DEFINE_FLAG
@@ -204,6 +199,10 @@ struct intel_device_info {
        struct {
                u8 ver;
 
+               u8 pipe_mask;
+               u8 cpu_transcoder_mask;
+               u8 abox_mask;
+
 #define DEFINE_FLAG(name) u8 name:1
                DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG);
 #undef DEFINE_FLAG