drm/xe: Fix WA 14010918519 write to wrong register

FORCE_SLM_FENCE_SCOPE_TO_TILE and FORCE_UGM_FENCE_SCOPE_TO_TILE are in
the up dword of LSC_CHICKEN_BIT_0 register. Also, the 14010918519
workaround only applies to early steppings, A*. Eventually those should
be dropped, like they were in commit eaeb4b361452 ("drm/i915/dg2: Drop
pre-production GT workarounds"), so let's make sure they are annotated
appropriately.

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20231024220412.223868-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index ccb075aac7da9af22ed7d66e5ca5635cc8e6bcb1..ce61609b001cbae860d1527967ffa1530fe2e3f7 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -367,9 +367,9 @@ static const struct xe_rtp_entry_sr engine_was[] = {
          XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, FORCE_1_SUB_MESSAGE_PER_FRAGMENT))
        },
        { XE_RTP_NAME("14010918519"),
-         XE_RTP_RULES(SUBPLATFORM(DG2, G10),
+         XE_RTP_RULES(SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0),
                       FUNC(xe_rtp_match_first_render_or_compute)),
-         XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0,
+         XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW,
                             FORCE_SLM_FENCE_SCOPE_TO_TILE |
                             FORCE_UGM_FENCE_SCOPE_TO_TILE,
                             /*