drm/i915/selftests: Set always_coherent to false when reading from CPU
authorNirmoy Das <nirmoy.das@intel.com>
Thu, 16 May 2024 15:14:03 +0000 (17:14 +0200)
committerJani Nikula <jani.nikula@intel.com>
Wed, 29 May 2024 08:35:32 +0000 (11:35 +0300)
Commit 8d4ba9fc1c6c ("drm/i915/selftests: Pick correct caching mode.")
was not complete  as for non LLC  sharing platforms cpu read can happen
from LLC which probably doesn't have the latest changes made by GPU.

Cc: Andi Shyti <andi.shyti@linux.intel.com>
Cc: Janusz Krzysztofik <janusz.krzysztofik@linux.intel.com>
Cc: Jonathan Cavitt <jonathan.cavitt@intel.com>
Fixes: 8d4ba9fc1c6c ("drm/i915/selftests: Pick correct caching mode.")
Reviewed-by: Jonathan Cavitt <jonathan.cavitt@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240516151403.2875-1-nirmoy.das@intel.com
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
(cherry picked from commit 007ed70831426d4cc108d879d688de6b8e3e6d45)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
drivers/gpu/drm/i915/gem/selftests/i915_gem_dmabuf.c

index 65a931ea80e9b846338b00f35951df2d0723f2e6..3527b8f446fe3b89978391c3de2d366eb252f536 100644 (file)
@@ -196,7 +196,7 @@ static int verify_access(struct drm_i915_private *i915,
        if (err)
                goto out_file;
 
-       mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, true);
+       mode = intel_gt_coherent_map_type(to_gt(i915), native_obj, false);
        vaddr = i915_gem_object_pin_map_unlocked(native_obj, mode);
        if (IS_ERR(vaddr)) {
                err = PTR_ERR(vaddr);