crypto/nx: Initialize 842 high and normal RxFIFO control registers

NX increments readOffset by FIFO size in receive FIFO control register
when CRB is read. But the index in RxFIFO has to match with the
corresponding entry in FIFO maintained by VAS in kernel. Otherwise NX
may be processing incorrect CRBs and can cause CRB timeout.

VAS FIFO offset is 0 when the receive window is opened during
initialization. When the module is reloaded or in kexec boot, readOffset
in FIFO control register may not match with VAS entry. This patch adds
nx_coproc_init OPAL call to reset readOffset and queued entries in FIFO
control register for both high and normal FIFOs.

Signed-off-by: Haren Myneni <haren@us.ibm.com>
[mpe: Fixup uninitialized variable warning]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/include/asm/opal-api.h b/arch/powerpc/include/asm/opal-api.h
index 56a94a1bd754202e59dd49e6500eff46ceb7fb29..8365353330b43e79f89fa9b55a00bc2a58ae5b06 100644 (file)
--- a/arch/powerpc/include/asm/opal-api.h
+++ b/arch/powerpc/include/asm/opal-api.h
@@ -209,7 +209,8 @@
 #define OPAL_SENSOR_GROUP_ENABLE               163
 #define OPAL_PCI_GET_PBCQ_TUNNEL_BAR           164
 #define OPAL_PCI_SET_PBCQ_TUNNEL_BAR           165
-#define OPAL_LAST                              165
+#define        OPAL_NX_COPROC_INIT                     167
+#define OPAL_LAST                              167
 
 #define QUIESCE_HOLD                   1 /* Spin all calls at entry */
 #define QUIESCE_REJECT                 2 /* Fail all calls with OPAL_BUSY */

diff --git a/arch/powerpc/include/asm/opal.h b/arch/powerpc/include/asm/opal.h
index 2e81555de64395d9fa9cf32a6c98204caa7289b4..834e7e29f1e4e0e9b948095aa8959e3f60d4be2a 100644 (file)
--- a/arch/powerpc/include/asm/opal.h
+++ b/arch/powerpc/include/asm/opal.h
@@ -293,6 +293,7 @@ int opal_get_power_shift_ratio(u32 handle, int token, u32 *psr);
 int opal_set_power_shift_ratio(u32 handle, int token, u32 psr);
 int opal_sensor_group_clear(u32 group_hndl, int token);
 int opal_sensor_group_enable(u32 group_hndl, int token, bool enable);
+int opal_nx_coproc_init(uint32_t chip_id, uint32_t ct);
 
 s64 opal_signal_system_reset(s32 cpu);
 s64 opal_quiesce(u64 shutdown_type, s32 cpu);

diff --git a/arch/powerpc/platforms/powernv/opal-wrappers.S b/arch/powerpc/platforms/powernv/opal-wrappers.S
index 029b37c04f357763d9f89ac0782a9dad3f6b3510..251528231a9e943b1318fc4f117163717f3d160c 100644 (file)
--- a/arch/powerpc/platforms/powernv/opal-wrappers.S
+++ b/arch/powerpc/platforms/powernv/opal-wrappers.S
@@ -330,3 +330,4 @@ OPAL_CALL(opal_pci_get_pbcq_tunnel_bar,             OPAL_PCI_GET_PBCQ_TUNNEL_BAR);
 OPAL_CALL(opal_pci_set_pbcq_tunnel_bar,                OPAL_PCI_SET_PBCQ_TUNNEL_BAR);
 OPAL_CALL(opal_sensor_read_u64,                        OPAL_SENSOR_READ_U64);
 OPAL_CALL(opal_sensor_group_enable,            OPAL_SENSOR_GROUP_ENABLE);
+OPAL_CALL(opal_nx_coproc_init,                 OPAL_NX_COPROC_INIT);

diff --git a/arch/powerpc/platforms/powernv/opal.c b/arch/powerpc/platforms/powernv/opal.c
index 46f58ff80bcf457804a64cdb9da42cab13e2529c..404c379db168cf614036293c8787c75b6b656d58 100644 (file)
--- a/arch/powerpc/platforms/powernv/opal.c
+++ b/arch/powerpc/platforms/powernv/opal.c
@@ -1090,3 +1090,5 @@ EXPORT_SYMBOL_GPL(opal_write_oppanel_async);
 EXPORT_SYMBOL_GPL(opal_int_set_mfrr);
 EXPORT_SYMBOL_GPL(opal_int_eoi);
 EXPORT_SYMBOL_GPL(opal_error_code);
+/* Export the below symbol for NX compression */
+EXPORT_SYMBOL(opal_nx_coproc_init);

diff --git a/drivers/crypto/nx/nx-842-powernv.c b/drivers/crypto/nx/nx-842-powernv.c
index 36afd6d8753c1a6207e3553c927ee1dbf989f199..c68df7e8bee185487cd6e9544fd6c4f31ab0a9c2 100644 (file)
--- a/drivers/crypto/nx/nx-842-powernv.c
+++ b/drivers/crypto/nx/nx-842-powernv.c
@@ -24,6 +24,8 @@
 #include <asm/icswx.h>
 #include <asm/vas.h>
 #include <asm/reg.h>
+#include <asm/opal-api.h>
+#include <asm/opal.h>
 
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Dan Streetman <ddstreet@ieee.org>");
@@ -753,7 +755,7 @@ static int nx842_open_percpu_txwins(void)
 }
 
 static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
-                                       int vasid)
+                                       int vasid, int *ct)
 {
        struct vas_window *rxwin = NULL;
        struct vas_rx_win_attr rxattr;
@@ -837,6 +839,15 @@ static int __init vas_cfg_coproc_info(struct device_node *dn, int chip_id,
        coproc->vas.id = vasid;
        nx842_add_coprocs_list(coproc, chip_id);
 
+       /*
+        * (lpid, pid, tid) combination has to be unique for each
+        * coprocessor instance in the system. So to make it
+        * unique, skiboot uses coprocessor type such as 842 or
+        * GZIP for pid and provides this value to kernel in pid
+        * device-tree property.
+        */
+       *ct = pid;
+
        return 0;
 
 err_out:
@@ -850,6 +861,7 @@ static int __init nx842_powernv_probe_vas(struct device_node *pn)
        struct device_node *dn;
        int chip_id, vasid, ret = 0;
        int nx_fifo_found = 0;
+       int uninitialized_var(ct);
 
        chip_id = of_get_ibm_chip_id(pn);
        if (chip_id < 0) {
@@ -865,7 +877,7 @@ static int __init nx842_powernv_probe_vas(struct device_node *pn)
 
        for_each_child_of_node(pn, dn) {
                if (of_device_is_compatible(dn, "ibm,p9-nx-842")) {
-                       ret = vas_cfg_coproc_info(dn, chip_id, vasid);
+                       ret = vas_cfg_coproc_info(dn, chip_id, vasid, &ct);
                        if (ret) {
                                of_node_put(dn);
                                return ret;
@@ -876,9 +888,22 @@ static int __init nx842_powernv_probe_vas(struct device_node *pn)
 
        if (!nx_fifo_found) {
                pr_err("NX842 FIFO nodes are missing\n");
-               ret = -EINVAL;
+               return -EINVAL;
        }
 
+       /*
+        * Initialize NX instance for both high and normal priority FIFOs.
+        */
+       if (opal_check_token(OPAL_NX_COPROC_INIT)) {
+               ret = opal_nx_coproc_init(chip_id, ct);
+               if (ret) {
+                       pr_err("Failed to initialize NX for chip(%d): %d\n",
+                               chip_id, ret);
+                       ret = opal_error_code(ret);
+               }
+       } else
+               pr_warn("Firmware doesn't support NX initialization\n");
+
        return ret;
 }