[media] s5p-csis: Allow to specify pixel clock's source through platform data
authorSylwester Nawrocki <s.nawrocki@samsung.com>
Mon, 17 Sep 2012 09:03:38 +0000 (06:03 -0300)
committerMauro Carvalho Chehab <mchehab@redhat.com>
Sat, 6 Oct 2012 01:35:16 +0000 (22:35 -0300)
Depending on the sensor configuration it might be required to adjust
the CSIS's output pixel clock so it is greater than its input pixel
clock, in order to avoid the input data FIFO overflow.
Use platform data to select SCLK_CSIS clock from CMU as a source, rather
than CSI APB clock.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@redhat.com>
drivers/media/platform/s5p-fimc/mipi-csis.c
include/linux/platform_data/mipi-csis.h

index 983e81f08cd6ddd5bfa40b1f7167f2e42611ffa8..4c961b1b68e6004ab1dd98d578b0e6cc407e97f9 100644 (file)
@@ -322,8 +322,10 @@ static void s5pcsis_set_params(struct csis_state *state)
                val |= S5PCSIS_CTRL_ALIGN_32BIT;
        else /* 24-bits */
                val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
-       /* Not using external clock. */
+
        val &= ~S5PCSIS_CTRL_WCLK_EXTCLK;
+       if (pdata->wclk_source)
+               val |= S5PCSIS_CTRL_WCLK_EXTCLK;
        s5pcsis_write(state, S5PCSIS_CTRL, val);
 
        /* Update the shadow register. */
index 8b703e1eeddfa69b55b15caa1608d30c77a9a58b..bf34e17cee7f6eb9c9068d811c37dae3b8c10fe0 100644 (file)
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2010-2011 Samsung Electronics Co., Ltd.
+ * Copyright (C) 2010 - 2012 Samsung Electronics Co., Ltd.
  *
  * Samsung S5P/Exynos SoC series MIPI CSIS device support
  *
 /**
  * struct s5p_platform_mipi_csis - platform data for S5P MIPI-CSIS driver
  * @clk_rate:    bus clock frequency
+ * @wclk_source: CSI wrapper clock selection: 0 - bus clock, 1 - ext. SCLK_CAM
  * @lanes:       number of data lanes used
  * @hs_settle:   HS-RX settle time
  */
 struct s5p_platform_mipi_csis {
        unsigned long clk_rate;
+       u8 wclk_source;
        u8 lanes;
        u8 hs_settle;
 };