Merge patch series "Zacas/Zabha support and qspinlocks"

Alexandre Ghiti <alexghiti@rivosinc.com> says:

This implements [cmp]xchgXX() macros using Zacas and Zabha extensions
and finally uses those newly introduced macros to add support for
qspinlocks: note that this implementation of qspinlocks satisfies the
forward progress guarantee.

It also uses Ziccrse to provide the qspinlock implementation.

Thanks to Guo and Leonardo for their work!

* b4-shazam-merge: (1314 commits)
  riscv: Add qspinlock support
  dt-bindings: riscv: Add Ziccrse ISA extension description
  riscv: Add ISA extension parsing for Ziccrse
  asm-generic: ticket-lock: Add separate ticket-lock.h
  asm-generic: ticket-lock: Reuse arch_spinlock_t of qspinlock
  riscv: Implement xchg8/16() using Zabha
  riscv: Implement arch_cmpxchg128() using Zacas
  riscv: Improve zacas fully-ordered cmpxchg()
  riscv: Implement cmpxchg8/16() using Zabha
  dt-bindings: riscv: Add Zabha ISA extension description
  riscv: Implement cmpxchg32/64() using Zacas
  riscv: Do not fail to build on byte/halfword operations with Zawrs
  riscv: Move cpufeature.h macros into their own header

Link: https://lore.kernel.org/r/20241103145153.105097-1-alexghiti@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>

diff --cc Documentation/devicetree/bindings/riscv/extensions.yaml
Simple merge

diff --cc arch/riscv/Kconfig
Simple merge

diff --cc arch/riscv/include/asm/cpufeature.h
index 04d7ab9eafe08ed80c822b5b9fa39e91584748ed,87ed88fc950da7629a2387b80f1a99ca25c8b25d..4bd054c54c21a3485e567727d3677fc41cef48db
--- 1/arch/riscv/include/asm/cpufeature.h
--- 2/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@@ -8,10 -8,11 +8,12 @@@
  
  #include <linux/bitmap.h>
  #include <linux/jump_label.h>
 +#include <linux/workqueue.h>
+ #include <linux/kconfig.h>
+ #include <linux/percpu-defs.h>
+ #include <linux/threads.h>
  #include <asm/hwcap.h>
- #include <asm/alternative-macros.h>
- #include <asm/errno.h>
+ #include <asm/cpufeature-macros.h>
  
  /*
   * These are probed via a device_initcall(), via either the SBI or directly

diff --cc arch/riscv/include/asm/hwcap.h
index 8608883da4539e06b9eb03983c20d802bc76a1de,0aa3c3f5e682b0ac6eda8f2d3f23d39438e4da4d..08d2a5697466d07fe2319a2423f04657177db37f
--- 1/arch/riscv/include/asm/hwcap.h
--- 2/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@@ -93,9 -93,8 +93,11 @@@
  #define RISCV_ISA_EXT_ZCMOP           84
  #define RISCV_ISA_EXT_ZAWRS           85
  #define RISCV_ISA_EXT_SVVPTC          86
 -#define RISCV_ISA_EXT_ZABHA           87
 -#define RISCV_ISA_EXT_ZICCRSE         88
 +#define RISCV_ISA_EXT_SMMPM           87
 +#define RISCV_ISA_EXT_SMNPM           88
 +#define RISCV_ISA_EXT_SSNPM           89
++#define RISCV_ISA_EXT_ZABHA           90
++#define RISCV_ISA_EXT_ZICCRSE         91
  
  #define RISCV_ISA_EXT_XLINUXENVCFG    127
  

diff --cc arch/riscv/kernel/cpufeature.c
Simple merge