arm64: dts: renesas: r8a779f0: Fix SCIF "brg_int" clock

As serial communication requires a clean clock signal, the Serial
Communication Interfaces with FIFO (SCIF) are clocked by a clock that is
not affected by Spread Spectrum or Fractional Multiplication.

Hence change the clock input for the SCIF Baud Rate Generator internal
clock from the S0D3_PER clock to the SASYNCPERD1 clock (which has the
same clock rate), cfr. R-Car S4-8 Hardware User's Manual rev. 0.81.

Fixes: c62331e8222f ("arm64: dts: renesas: Add Renesas R8A779F0 SoC support")
Fixes: 40753144256b ("arm64: dts: renesas: r8a779f0: Add SCIF nodes")
Reported-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20221103143440.46449-5-wsa+renesas@sang-engineering.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index 3be577dc9a9314ea19c202e1714df5628021c198..4092c0016035ebf7adfd7aa59f9612cc98c1687a 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -657,7 +657,7 @@
                        reg = <0 0xe6e60000 0 64>;
                        interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 702>,
-                                <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
                                 <&scif_clk>;
                        clock-names = "fck", "brg_int", "scif_clk";
                        dmas = <&dmac0 0x51>, <&dmac0 0x50>,
@@ -674,7 +674,7 @@
                        reg = <0 0xe6e68000 0 64>;
                        interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 703>,
-                                <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
                                 <&scif_clk>;
                        clock-names = "fck", "brg_int", "scif_clk";
                        dmas = <&dmac0 0x53>, <&dmac0 0x52>,
@@ -691,7 +691,7 @@
                        reg = <0 0xe6c50000 0 64>;
                        interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 704>,
-                                <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
                                 <&scif_clk>;
                        clock-names = "fck", "brg_int", "scif_clk";
                        dmas = <&dmac0 0x57>, <&dmac0 0x56>,
@@ -708,7 +708,7 @@
                        reg = <0 0xe6c40000 0 64>;
                        interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&cpg CPG_MOD 705>,
-                                <&cpg CPG_CORE R8A779F0_CLK_S0D3_PER>,
+                                <&cpg CPG_CORE R8A779F0_CLK_SASYNCPERD1>,
                                 <&scif_clk>;
                        clock-names = "fck", "brg_int", "scif_clk";
                        dmas = <&dmac0 0x59>, <&dmac0 0x58>,