drm/amdgpu/vcn: adjust pause_dpg_mode function signature
authorAlex Deucher <alexander.deucher@amd.com>
Tue, 26 Nov 2024 16:14:58 +0000 (11:14 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 27 Feb 2025 20:52:30 +0000 (15:52 -0500)
Change it to take a vcn instance rather than adev to align
with the vcn instance changes.

TODO: clean up the function internals to use the vinst state
directly rather than accessing it indirectly via adev->vcn.inst[].

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.c
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v4_0.c
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.c
drivers/gpu/drm/amd/amdgpu/vcn_v4_0_5.c
drivers/gpu/drm/amd/amdgpu/vcn_v5_0_0.c

index 010cc64a950a4cc7a8751374b9c2c3533fa291a3..a2250747a7c813af744c9628b00548a0f1da6559 100644 (file)
@@ -417,7 +417,7 @@ static void amdgpu_vcn_idle_work_handler(struct work_struct *work)
                else
                        new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
 
-               adev->vcn.inst[i].pause_dpg_mode(adev, i, &new_state);
+               adev->vcn.inst[i].pause_dpg_mode(vcn_inst, &new_state);
        }
 
        fence[i] += amdgpu_fence_count_emitted(&vcn_inst->ring_dec);
@@ -474,7 +474,7 @@ void amdgpu_vcn_ring_begin_use(struct amdgpu_ring *ring)
                                new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
                }
 
-               adev->vcn.inst[ring->me].pause_dpg_mode(adev, ring->me, &new_state);
+               adev->vcn.inst[ring->me].pause_dpg_mode(&adev->vcn.inst[ring->me], &new_state);
        }
        mutex_unlock(&adev->vcn.inst[ring->me].vcn_pg_lock);
 }
index 5f92cf28cc752c8a33e3c98ccfd9250d50d1d209..8d34e3814ab198819e7476d2b803bb194d4ed009 100644 (file)
@@ -327,8 +327,7 @@ struct amdgpu_vcn_inst {
        bool                    indirect_sram;
        struct amdgpu_vcn_reg    internal;
        struct mutex            vcn1_jpeg1_workaround;
-       int (*pause_dpg_mode)(struct amdgpu_device *adev,
-                             int inst_idx,
+       int (*pause_dpg_mode)(struct amdgpu_vcn_inst *vinst,
                              struct dpg_pause_state *new_state);
        bool using_unified_queue;
 };
index 267bfc32284ca28e86d34d702683ac06eacbe906..9c583ae0ff7e049fbfe24163aafa07ce263e7f1b 100644 (file)
@@ -87,8 +87,8 @@ static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
 static int vcn_v1_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                enum amd_powergating_state state);
-static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
-                               int inst_idx, struct dpg_pause_state *new_state);
+static int vcn_v1_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                  struct dpg_pause_state *new_state);
 
 static void vcn_v1_0_idle_work_handler(struct work_struct *work);
 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
@@ -1264,9 +1264,11 @@ static int vcn_v1_0_stop(struct amdgpu_vcn_inst *vinst)
        return r;
 }
 
-static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
-                               int inst_idx, struct dpg_pause_state *new_state)
+static int vcn_v1_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                  struct dpg_pause_state *new_state)
 {
+       struct amdgpu_device *adev = vinst->adev;
+       int inst_idx = vinst->inst;
        int ret_code;
        uint32_t reg_data = 0;
        uint32_t reg_data2 = 0;
@@ -1866,7 +1868,7 @@ static void vcn_v1_0_idle_work_handler(struct work_struct *work)
                else
                        new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
 
-               adev->vcn.inst[0].pause_dpg_mode(adev, 0, &new_state);
+               adev->vcn.inst->pause_dpg_mode(vcn_inst, &new_state);
        }
 
        fences += amdgpu_fence_count_emitted(adev->jpeg.inst->ring_dec);
@@ -1933,7 +1935,7 @@ void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
                else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
                        new_state.jpeg = VCN_DPG_STATE__PAUSE;
 
-               adev->vcn.inst[0].pause_dpg_mode(adev, 0, &new_state);
+               adev->vcn.inst->pause_dpg_mode(adev->vcn.inst, &new_state);
        }
 }
 
index 43672ba236e3caf7dc5ff02ec9177a3c691536da..506b070be3ec75cce97e95744f7c0e2838c96190 100644 (file)
@@ -94,8 +94,8 @@ static void vcn_v2_0_set_enc_ring_funcs(struct amdgpu_device *adev);
 static void vcn_v2_0_set_irq_funcs(struct amdgpu_device *adev);
 static int vcn_v2_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                enum amd_powergating_state state);
-static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
-                               int inst_idx, struct dpg_pause_state *new_state);
+static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                  struct dpg_pause_state *new_state);
 static int vcn_v2_0_start_sriov(struct amdgpu_device *adev);
 /**
  * vcn_v2_0_early_init - set function pointers and load microcode
@@ -1158,7 +1158,7 @@ static int vcn_v2_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
        struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
        uint32_t tmp;
 
-       vcn_v2_0_pause_dpg_mode(adev, 0, &state);
+       vcn_v2_0_pause_dpg_mode(vinst, &state);
        /* Wait for power status to be 1 */
        SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS, 1,
                UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
@@ -1252,9 +1252,11 @@ power_off:
        return 0;
 }
 
-static int vcn_v2_0_pause_dpg_mode(struct amdgpu_device *adev,
-                               int inst_idx, struct dpg_pause_state *new_state)
+static int vcn_v2_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                  struct dpg_pause_state *new_state)
 {
+       struct amdgpu_device *adev = vinst->adev;
+       int inst_idx = vinst->inst;
        struct amdgpu_ring *ring;
        uint32_t reg_data = 0;
        int ret_code;
index 5df2decd9d793b171d3304808dedabe2de85fd67..9752f99297df5e160bebe1ea3909307fb1e10726 100644 (file)
@@ -100,8 +100,8 @@ static int vcn_v2_5_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
                                               int i);
 static int vcn_v2_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state);
-static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
-                               int inst_idx, struct dpg_pause_state *new_state);
+static int vcn_v2_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                  struct dpg_pause_state *new_state);
 static int vcn_v2_5_sriov_start(struct amdgpu_device *adev);
 static void vcn_v2_5_set_ras_funcs(struct amdgpu_device *adev);
 
@@ -1510,9 +1510,11 @@ done:
        return r;
 }
 
-static int vcn_v2_5_pause_dpg_mode(struct amdgpu_device *adev,
-                               int inst_idx, struct dpg_pause_state *new_state)
+static int vcn_v2_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                  struct dpg_pause_state *new_state)
 {
+       struct amdgpu_device *adev = vinst->adev;
+       int inst_idx = vinst->inst;
        struct amdgpu_ring *ring;
        uint32_t reg_data = 0;
        int ret_code = 0;
index 2fd58d548b19eea88a9675eee49436d36eeb8cd0..7e98f251f23e6ed6844ae79ec1323ca37ec4043e 100644 (file)
@@ -110,8 +110,8 @@ static int vcn_v3_0_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
                                               int i);
 static int vcn_v3_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state);
-static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
-                       int inst_idx, struct dpg_pause_state *new_state);
+static int vcn_v3_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                  struct dpg_pause_state *new_state);
 
 static void vcn_v3_0_dec_ring_set_wptr(struct amdgpu_ring *ring);
 static void vcn_v3_0_enc_ring_set_wptr(struct amdgpu_ring *ring);
@@ -1581,7 +1581,7 @@ static int vcn_v3_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
        struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
        uint32_t tmp;
 
-       vcn_v3_0_pause_dpg_mode(adev, inst_idx, &state);
+       vcn_v3_0_pause_dpg_mode(vinst, &state);
 
        /* Wait for power status to be 1 */
        SOC15_WAIT_ON_RREG(VCN, inst_idx, mmUVD_POWER_STATUS, 1,
@@ -1683,9 +1683,11 @@ done:
        return r;
 }
 
-static int vcn_v3_0_pause_dpg_mode(struct amdgpu_device *adev,
-                  int inst_idx, struct dpg_pause_state *new_state)
+static int vcn_v3_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                  struct dpg_pause_state *new_state)
 {
+       struct amdgpu_device *adev = vinst->adev;
+       int inst_idx = vinst->inst;
        volatile struct amdgpu_fw_shared *fw_shared;
        struct amdgpu_ring *ring;
        uint32_t reg_data = 0;
index 0e6af9be0d3c99d74547e4c70dd9c7e4d6290b07..41ec696bd2102a26009fefc17748f138bd8dc1a7 100644 (file)
@@ -101,8 +101,8 @@ static int vcn_v4_0_set_powergating_state_inst(struct amdgpu_ip_block *ip_block,
                                               int i);
 static int vcn_v4_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                          enum amd_powergating_state state);
-static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev,
-        int inst_idx, struct dpg_pause_state *new_state);
+static int vcn_v4_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                  struct dpg_pause_state *new_state);
 static void vcn_v4_0_unified_ring_set_wptr(struct amdgpu_ring *ring);
 static void vcn_v4_0_set_ras_funcs(struct amdgpu_device *adev);
 
@@ -1565,7 +1565,7 @@ static void vcn_v4_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
        struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
        uint32_t tmp;
 
-       vcn_v4_0_pause_dpg_mode(adev, inst_idx, &state);
+       vcn_v4_0_pause_dpg_mode(vinst, &state);
        /* Wait for power status to be 1 */
        SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
                UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
@@ -1673,15 +1673,16 @@ done:
 /**
  * vcn_v4_0_pause_dpg_mode - VCN pause with dpg mode
  *
- * @adev: amdgpu_device pointer
- * @inst_idx: instance number index
+ * @vinst: VCN instance
  * @new_state: pause state
  *
  * Pause dpg mode for VCN block
  */
-static int vcn_v4_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
-      struct dpg_pause_state *new_state)
+static int vcn_v4_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                  struct dpg_pause_state *new_state)
 {
+       struct amdgpu_device *adev = vinst->adev;
+       int inst_idx = vinst->inst;
        uint32_t reg_data = 0;
        int ret_code;
 
index 9e1c25210f880bc384f978143cbd8de7e5046540..e681e0939eeb5df94ed7f7946294b4923865677f 100644 (file)
@@ -92,8 +92,8 @@ static int vcn_v4_0_3_set_powergating_state_inst(struct amdgpu_ip_block *ip_bloc
                                                 int i);
 static int vcn_v4_0_3_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                            enum amd_powergating_state state);
-static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev,
-               int inst_idx, struct dpg_pause_state *new_state);
+static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                    struct dpg_pause_state *new_state);
 static void vcn_v4_0_3_unified_ring_set_wptr(struct amdgpu_ring *ring);
 static void vcn_v4_0_3_set_ras_funcs(struct amdgpu_device *adev);
 static void vcn_v4_0_3_enable_ras(struct amdgpu_device *adev,
@@ -1443,14 +1443,13 @@ Done:
 /**
  * vcn_v4_0_3_pause_dpg_mode - VCN pause with dpg mode
  *
- * @adev: amdgpu_device pointer
- * @inst_idx: instance number index
+ * @vinst: VCN instance
  * @new_state: pause state
  *
  * Pause dpg mode for VCN block
  */
-static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
-                               struct dpg_pause_state *new_state)
+static int vcn_v4_0_3_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                    struct dpg_pause_state *new_state)
 {
 
        return 0;
index 9b5c6812a0b45e831ea2759138df5d98875373c7..3e2206e5e0e126526dec18054a97aa076fa5addd 100644 (file)
@@ -100,8 +100,8 @@ static int vcn_v4_0_5_set_powergating_state_inst(struct amdgpu_ip_block *ip_bloc
                                                 int i);
 static int vcn_v4_0_5_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                            enum amd_powergating_state state);
-static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev,
-               int inst_idx, struct dpg_pause_state *new_state);
+static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                    struct dpg_pause_state *new_state);
 static void vcn_v4_0_5_unified_ring_set_wptr(struct amdgpu_ring *ring);
 
 /**
@@ -1323,15 +1323,16 @@ done:
 /**
  * vcn_v4_0_5_pause_dpg_mode - VCN pause with dpg mode
  *
- * @adev: amdgpu_device pointer
- * @inst_idx: instance number index
+ * @vinst: VCN instance
  * @new_state: pause state
  *
  * Pause dpg mode for VCN block
  */
-static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
-               struct dpg_pause_state *new_state)
+static int vcn_v4_0_5_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                    struct dpg_pause_state *new_state)
 {
+       struct amdgpu_device *adev = vinst->adev;
+       int inst_idx = vinst->inst;
        uint32_t reg_data = 0;
        int ret_code;
 
index 288be78280dd93dc515cb54f431f83e7c2fc928c..ec57c7dd78bfbbc1dcb2538787eed2094b4b1f71 100644 (file)
@@ -83,8 +83,8 @@ static int vcn_v5_0_0_set_powergating_state_inst(struct amdgpu_ip_block *ip_bloc
                                                 int i);
 static int vcn_v5_0_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
                                            enum amd_powergating_state state);
-static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev,
-               int inst_idx, struct dpg_pause_state *new_state);
+static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                    struct dpg_pause_state *new_state);
 static void vcn_v5_0_0_unified_ring_set_wptr(struct amdgpu_ring *ring);
 
 /**
@@ -961,7 +961,7 @@ static void vcn_v5_0_0_stop_dpg_mode(struct amdgpu_vcn_inst *vinst)
        struct dpg_pause_state state = {.fw_based = VCN_DPG_STATE__UNPAUSE};
        uint32_t tmp;
 
-       vcn_v5_0_0_pause_dpg_mode(adev, inst_idx, &state);
+       vcn_v5_0_0_pause_dpg_mode(vinst, &state);
 
        /* Wait for power status to be 1 */
        SOC15_WAIT_ON_RREG(VCN, inst_idx, regUVD_POWER_STATUS, 1,
@@ -1066,15 +1066,16 @@ done:
 /**
  * vcn_v5_0_0_pause_dpg_mode - VCN pause with dpg mode
  *
- * @adev: amdgpu_device pointer
- * @inst_idx: instance number index
+ * @vinst: VCN instance
  * @new_state: pause state
  *
  * Pause dpg mode for VCN block
  */
-static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_device *adev, int inst_idx,
-       struct dpg_pause_state *new_state)
+static int vcn_v5_0_0_pause_dpg_mode(struct amdgpu_vcn_inst *vinst,
+                                    struct dpg_pause_state *new_state)
 {
+       struct amdgpu_device *adev = vinst->adev;
+       int inst_idx = vinst->inst;
        uint32_t reg_data = 0;
        int ret_code;