drm/amd/display: increase dcn315 pstate change latency

[Why & How]
Update after new measurment came in

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Wayne Lin <wayne.lin@amd.com>
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index 7f481ab252d0abfab8ca41dd88d3f364b59e2a32..893991a0eb9711d2a9fd4701834c4d3d0473ba61 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -51,6 +51,9 @@
 #define TO_CLK_MGR_DCN315(clk_mgr)\
        container_of(clk_mgr, struct clk_mgr_dcn315, base)
 
+#define UNSUPPORTED_DCFCLK 10000000
+#define MIN_DPP_DISP_CLK     100000
+
 static int dcn315_get_active_display_cnt_wa(
                struct dc *dc,
                struct dc_state *context)
@@ -152,6 +155,9 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
                }
        }
 
+       /* Lock pstate by requesting unsupported dcfclk if change is unsupported */
+       if (!new_clocks->p_state_change_support)
+               new_clocks->dcfclk_khz = UNSUPPORTED_DCFCLK;
        if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
                clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
                dcn315_smu_set_hard_min_dcfclk(clk_mgr, clk_mgr_base->clks.dcfclk_khz);
@@ -165,10 +171,10 @@ static void dcn315_update_clocks(struct clk_mgr *clk_mgr_base,
 
        // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow.
        if (!IS_DIAG_DC(dc->ctx->dce_environment)) {
-               if (new_clocks->dppclk_khz < 100000)
-                       new_clocks->dppclk_khz = 100000;
-               if (new_clocks->dispclk_khz < 100000)
-                       new_clocks->dispclk_khz = 100000;
+               if (new_clocks->dppclk_khz < MIN_DPP_DISP_CLK)
+                       new_clocks->dppclk_khz = MIN_DPP_DISP_CLK;
+               if (new_clocks->dispclk_khz < MIN_DPP_DISP_CLK)
+                       new_clocks->dispclk_khz = MIN_DPP_DISP_CLK;
        }
 
        if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr->base.clks.dppclk_khz)) {
@@ -281,7 +287,7 @@ static struct wm_table ddr5_wm_table = {
                {
                        .wm_inst = WM_A,
                        .wm_type = WM_TYPE_PSTATE_CHG,
-                       .pstate_latency_us = 64.0,
+                       .pstate_latency_us = 129.0,
                        .sr_exit_time_us = 11.5,
                        .sr_enter_plus_exit_time_us = 14.5,
                        .valid = true,
@@ -289,7 +295,7 @@ static struct wm_table ddr5_wm_table = {
                {
                        .wm_inst = WM_B,
                        .wm_type = WM_TYPE_PSTATE_CHG,
-                       .pstate_latency_us = 64.0,
+                       .pstate_latency_us = 129.0,
                        .sr_exit_time_us = 11.5,
                        .sr_enter_plus_exit_time_us = 14.5,
                        .valid = true,
@@ -297,7 +303,7 @@ static struct wm_table ddr5_wm_table = {
                {
                        .wm_inst = WM_C,
                        .wm_type = WM_TYPE_PSTATE_CHG,
-                       .pstate_latency_us = 64.0,
+                       .pstate_latency_us = 129.0,
                        .sr_exit_time_us = 11.5,
                        .sr_enter_plus_exit_time_us = 14.5,
                        .valid = true,
@@ -305,7 +311,7 @@ static struct wm_table ddr5_wm_table = {
                {
                        .wm_inst = WM_D,
                        .wm_type = WM_TYPE_PSTATE_CHG,
-                       .pstate_latency_us = 64.0,
+                       .pstate_latency_us = 129.0,
                        .sr_exit_time_us = 11.5,
                        .sr_enter_plus_exit_time_us = 14.5,
                        .valid = true,