drm/amd/display: Remove unused dm_pp_ interfaces

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 56e5492491342bfc6d537271d9ccfe379087c060..89342b48be6b4a6f0b88974e95cce241570958e1 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -71,15 +71,6 @@ bool dm_read_persistent_data(struct dc_context *ctx,
 
 /**** power component interfaces ****/
 
-bool dm_pp_pre_dce_clock_change(
-               struct dc_context *ctx,
-               struct dm_pp_gpu_clock_range *requested_state,
-               struct dm_pp_gpu_clock_range *actual_state)
-{
-       /*TODO*/
-       return false;
-}
-
 bool dm_pp_apply_display_requirements(
                const struct dc_context *ctx,
                const struct dm_pp_display_configuration *pp_display_cfg)
@@ -151,30 +142,6 @@ bool dm_pp_apply_display_requirements(
        return true;
 }
 
-bool dc_service_get_system_clocks_range(
-               const struct dc_context *ctx,
-               struct dm_pp_gpu_clock_range *sys_clks)
-{
-       struct amdgpu_device *adev = ctx->driver_context;
-
-       /* Default values, in case PPLib is not compiled-in. */
-       sys_clks->mclk.max_khz = 800000;
-       sys_clks->mclk.min_khz = 800000;
-
-       sys_clks->sclk.max_khz = 600000;
-       sys_clks->sclk.min_khz = 300000;
-
-       if (adev->pm.dpm_enabled) {
-               sys_clks->mclk.max_khz = amdgpu_dpm_get_mclk(adev, false);
-               sys_clks->mclk.min_khz = amdgpu_dpm_get_mclk(adev, true);
-
-               sys_clks->sclk.max_khz = amdgpu_dpm_get_sclk(adev, false);
-               sys_clks->sclk.min_khz = amdgpu_dpm_get_sclk(adev, true);
-       }
-
-       return true;
-}
-
 static void get_default_clock_levels(
                enum dm_pp_clock_type clk_type,
                struct dm_pp_clock_levels *clks)

diff --git a/drivers/gpu/drm/amd/display/dc/dm_services.h b/drivers/gpu/drm/amd/display/dc/dm_services.h
index 225b7bfb09a98484ee1efbb48fbd805b017063ee..22e7ee7dcd26d1b5cd1cb52afb8a5be55c464b6c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dm_services.h
+++ b/drivers/gpu/drm/amd/display/dc/dm_services.h
@@ -192,37 +192,6 @@ unsigned int generic_reg_wait(const struct dc_context *ctx,
  * Power Play (PP) interfaces
  **************************************/
 
-/* DAL calls this function to notify PP about clocks it needs for the Mode Set.
- * This is done *before* it changes DCE clock.
- *
- * If required clock is higher than current, then PP will increase the voltage.
- *
- * If required clock is lower than current, then PP will defer reduction of
- * voltage until the call to dc_service_pp_post_dce_clock_change().
- *
- * \input - Contains clocks needed for Mode Set.
- *
- * \output - Contains clocks adjusted by PP which DAL should use for Mode Set.
- *             Valid only if function returns zero.
- *
- * \returns    true - call is successful
- *             false - call failed
- */
-bool dm_pp_pre_dce_clock_change(
-       struct dc_context *ctx,
-       struct dm_pp_gpu_clock_range *requested_state,
-       struct dm_pp_gpu_clock_range *actual_state);
-
-/* The returned clocks range are 'static' system clocks which will be used for
- * mode validation purposes.
- *
- * \returns    true - call is successful
- *             false - call failed
- */
-bool dc_service_get_system_clocks_range(
-       const struct dc_context *ctx,
-       struct dm_pp_gpu_clock_range *sys_clks);
-
 /* Gets valid clocks levels from pplib
  *
  * input: clk_type - display clk / sclk / mem clk