drm/amdgpu: fix gart.bo pin_count leak
authorLeslie Shi <Yuliang.Shi@amd.com>
Thu, 23 Sep 2021 08:05:31 +0000 (16:05 +0800)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Sun, 17 Oct 2021 08:43:33 +0000 (10:43 +0200)
[ Upstream commit 66805763a97f8f7bdf742fc0851d85c02ed9411f ]

gmc_v{9,10}_0_gart_disable() isn't called matched with
correspoding gart_enbale function in SRIOV case. This will
lead to gart.bo pin_count leak on driver unload.

Cc: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Leslie Shi <Yuliang.Shi@amd.com>
Signed-off-by: Guchun Chen <guchun.chen@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c

index dbc8b76b9b78e650524775b95b3b1f06aae69ba6..150fa5258fb6fc0d0e783bfc4cb2c0c2b922bd1b 100644 (file)
@@ -1018,6 +1018,8 @@ static int gmc_v10_0_hw_fini(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+       gmc_v10_0_gart_disable(adev);
+
        if (amdgpu_sriov_vf(adev)) {
                /* full access mode, so don't touch any GMC register */
                DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
@@ -1026,7 +1028,6 @@ static int gmc_v10_0_hw_fini(void *handle)
 
        amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
        amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
-       gmc_v10_0_gart_disable(adev);
 
        return 0;
 }
index 3ebbddb63705cfa457dd03327d48b8892a6bb007..3a864041968f64bff614861c03bb0b860a892782 100644 (file)
@@ -1677,6 +1677,8 @@ static int gmc_v9_0_hw_fini(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+       gmc_v9_0_gart_disable(adev);
+
        if (amdgpu_sriov_vf(adev)) {
                /* full access mode, so don't touch any GMC register */
                DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
@@ -1685,7 +1687,6 @@ static int gmc_v9_0_hw_fini(void *handle)
 
        amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
        amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
-       gmc_v9_0_gart_disable(adev);
 
        return 0;
 }