drm/amd/amdgpu: Fix offset for SQ_DEBUG_STS_GLOBAL on gfx10 (v2)
authorTom St Denis <tom.stdenis@amd.com>
Tue, 16 Jun 2020 12:47:04 +0000 (08:47 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Jul 2020 05:59:22 +0000 (01:59 -0400)
Despite having different IP offsets the computed address of the register(s)
are the same between gfx7..gfx10.  This patch fixes the offset relative
to the GC block on gfx10.

(v2): SQ_DEBUG_STS_GLOBAL2 is 0x10 higher ...

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_1_0_offset.h
drivers/gpu/drm/amd/include/asic_reg/gc/gc_10_3_0_offset.h

index baac40fa70e7bf4a3e82fdca0a15fdb0f20642b7..18d34bbceebeeb2a8ad51b5f74cd33f6961a3116 100644 (file)
@@ -21,9 +21,9 @@
 #ifndef _gc_10_1_0_OFFSET_HEADER
 #define _gc_10_1_0_OFFSET_HEADER
 
-#define mmSQ_DEBUG_STS_GLOBAL                                                                          0x0309
+#define mmSQ_DEBUG_STS_GLOBAL                                                                          0x10A9
 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX                                                                 0
-#define mmSQ_DEBUG_STS_GLOBAL2                                                                         0x0310
+#define mmSQ_DEBUG_STS_GLOBAL2                                                                         0x10B0
 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX                                                                0
 
 // addressBlock: gc_sdma0_sdma0dec
index 0bde3b4e9567f832ed9585a41dbe16bb1ad06184..05d1b0a5f6d25f4259cd3f0d8366f16e2939ea44 100644 (file)
@@ -22,9 +22,9 @@
 #ifndef _gc_10_3_0_OFFSET_HEADER
 #define _gc_10_3_0_OFFSET_HEADER
 
-#define mmSQ_DEBUG_STS_GLOBAL                                                                          0x0309
+#define mmSQ_DEBUG_STS_GLOBAL                                                                          0x10A9
 #define mmSQ_DEBUG_STS_GLOBAL_BASE_IDX                                                                 0
-#define mmSQ_DEBUG_STS_GLOBAL2                                                                         0x0310
+#define mmSQ_DEBUG_STS_GLOBAL2                                                                         0x10B0
 #define mmSQ_DEBUG_STS_GLOBAL2_BASE_IDX                                                                0
 
 // addressBlock: gc_sdma0_sdma0dec