drm/amd/display: Set i2c memory to light sleep during hw init

[WHY]
i2c memory doesn't get set to light sleep on hw init as intended

[HOW]
Set i2c to light sleep after reg gets zeroed, ensuring memory power
control doesn't get disabled for any other DIO memory

Reviewed-by: Haonan Wang <Haonan.Wang2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Acked-by: Agustin Gutierrez <agustin.gutierrez@amd.com>
Signed-off-by: Michael Strauss <michael.strauss@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
index 296b2f80a1ecae77d65497be35a01c2cd7b73539..989f5b6907e21fa9333cf944d0ff9b4b523fac20 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
@@ -1151,7 +1151,8 @@ struct dce_hwseq_registers {
        type DOMAIN_POWER_GATE;\
        type DOMAIN_PGFSM_PWR_STATUS;\
        type HPO_HDMISTREAMCLK_G_GATE_DIS;\
-       type DISABLE_HOSTVM_FORCE_ALLOW_PSTATE;
+       type DISABLE_HOSTVM_FORCE_ALLOW_PSTATE;\
+       type I2C_LIGHT_SLEEP_FORCE;
 
 struct dce_hwseq_shift {
        HWSEQ_REG_FIELD_LIST(uint8_t)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
index 9a6ad1cebc857f7923d998273f1f357720329216..d24ad7754d710a72d6cb602c6ff54c7e7992ca6a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c
@@ -50,6 +50,7 @@
 #include "dcn10/dcn10_hw_sequencer.h"
 #include "inc/link_enc_cfg.h"
 #include "dcn30/dcn30_vpg.h"
+#include "dce/dce_i2c_hw.h"
 
 #define DC_LOGGER_INIT(logger)
 
@@ -259,6 +260,10 @@ void dcn31_init_hw(struct dc *dc)
        /* power AFMT HDMI memory TODO: may move to dis/en output save power*/
        REG_WRITE(DIO_MEM_PWR_CTRL, 0);
 
+       // Set i2c to light sleep until engine is setup
+       if (dc->debug.enable_mem_low_power.bits.i2c)
+               REG_UPDATE(DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, 1);
+
        if (!dc->debug.disable_clock_gate) {
                /* enable all DCN clock gating */
                REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
index 2b4459909648e681070513ddd3002b6a21c4bb84..4f60b36000cbb62b782a2bae22107352bb66688b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_resource.c
@@ -899,7 +899,8 @@ static const struct dce_hwseq_registers hwseq_reg = {
        HWS_SF(, DMU_MEM_PWR_CNTL, DMCU_ERAM_MEM_PWR_FORCE, mask_sh), \
        HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
        HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh), \
-       HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh)
+       HWS_SF(, MMHUBBUB_MEM_PWR_CNTL, VGA_MEM_PWR_FORCE, mask_sh), \
+       HWS_SF(, DIO_MEM_PWR_CTRL, I2C_LIGHT_SLEEP_FORCE, mask_sh)
 
 static const struct dce_hwseq_shift hwseq_shift = {
                HWSEQ_DCN31_MASK_SH_LIST(__SHIFT)