drm/i915/mtl: add initial definitions for GSC CS

Starting on MTL, the GSC is no longer managed with direct MMIO access,
but we instead have a dedicated command streamer for it. As a first step
for adding support for this CS, add the required definitions.
Note that, although it is now a CS, the GSC retains its old
class:instance value (OTHER_CLASS instance 6)

Bspec: 65308, 45605
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20221102171047.2787951-2-daniele.ceraolospurio@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3b7d750ad0541043da6b45974992ee24c67282e7..e0fbfac03979727732576c7521c778b2366cabbe 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -244,6 +244,13 @@ static const struct engine_info intel_engines[] = {
                        { .graphics_ver = 12, .base = GEN12_COMPUTE3_RING_BASE }
                }
        },
+       [GSC0] = {
+               .class = OTHER_CLASS,
+               .instance = OTHER_GSC_INSTANCE,
+               .mmio_bases = {
+                       { .graphics_ver = 12, .base = MTL_GSC_RING_BASE }
+               }
+       },
 };
 
 /**
@@ -324,6 +331,7 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
        case VIDEO_DECODE_CLASS:
        case VIDEO_ENHANCEMENT_CLASS:
        case COPY_ENGINE_CLASS:
+       case OTHER_CLASS:
                if (GRAPHICS_VER(gt->i915) < 8)
                        return 0;
                return GEN8_LR_CONTEXT_OTHER_SIZE;

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index 6b5d4ea22b673bacf320b18aa477de2466ee4171..4fd54fb8810fb1a1cc862d20d66d03f33c8e0312 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -136,6 +136,7 @@ enum intel_engine_id {
        CCS2,
        CCS3,
 #define _CCS(n) (CCS0 + (n))
+       GSC0,
        I915_NUM_ENGINES
 #define INVALID_ENGINE ((enum intel_engine_id)-1)
 };

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 46a174f8aa0076ca71926b23df17f2983ae347ce..79312b7346909ac811843df4d4f0744701524c92 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -140,6 +140,7 @@ const char *intel_engine_class_repr(u8 class)
                [COPY_ENGINE_CLASS] = "bcs",
                [VIDEO_DECODE_CLASS] = "vcs",
                [VIDEO_ENHANCEMENT_CLASS] = "vecs",
+               [OTHER_CLASS] = "other",
                [COMPUTE_CLASS] = "ccs",
        };
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1c0da50c0dc73589714047c47aab60343295f3f1..d056c3117ef2b940fa7f5e726c3436104e62f11b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -970,6 +970,7 @@
 #define GEN11_VEBOX2_RING_BASE         0x1d8000
 #define XEHP_VEBOX3_RING_BASE          0x1e8000
 #define XEHP_VEBOX4_RING_BASE          0x1f8000
+#define MTL_GSC_RING_BASE              0x11a000
 #define GEN12_COMPUTE0_RING_BASE       0x1a000
 #define GEN12_COMPUTE1_RING_BASE       0x1c000
 #define GEN12_COMPUTE2_RING_BASE       0x1e000