drm/radeon: apply more strict limits for PLL params v2
authorChristian König <christian.koenig@amd.com>
Fri, 4 Apr 2014 11:45:42 +0000 (13:45 +0200)
committerChristian König <christian.koenig@amd.com>
Thu, 17 Apr 2014 11:59:46 +0000 (13:59 +0200)
Letting post and refernce divider get to big is bad for signal stability.

v2: increase the limit to 210

Signed-off-by: Christian König <christian.koenig@amd.com>
drivers/gpu/drm/radeon/radeon_display.c

index 386cfa4c194dc40a75e13e23dde2adf040e029f2..2f42912031ac976a9250a080837efb91b1e5dc13 100644 (file)
@@ -937,6 +937,9 @@ void radeon_compute_pll_avivo(struct radeon_pll *pll,
        }
        post_div = post_div_best;
 
+       /* limit reference * post divider to a maximum */
+       ref_div_max = min(210 / post_div, ref_div_max);
+
        /* get matching reference and feedback divider */
        ref_div = max(den / post_div, 1u);
        fb_div = nom;