drm/amdgpu: correct ip for mmHDP_READ_CACHE_INVALIDATE register access

Use the proper IP index for HDP registers.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c
index 232adf83a7bf3c76f893b536b4ebb2ba4621f379..a076001b326d9c9f8db01ddf8e1b321583c329b0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/soc15.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc15.c
@@ -703,7 +703,7 @@ static void soc15_invalidate_hdp(struct amdgpu_device *adev,
                                 struct amdgpu_ring *ring)
 {
        if (!ring || !ring->funcs->emit_wreg)
-               WREG32_SOC15_NO_KIQ(NBIO, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
+               WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
        else
                amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
                        HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);