drm/amd/display: Enable DCN clock gating for DCN35

[WHY & HOW]
Enable DCN clock gating for DCN35.
Disable DTBCLK gate before link training
and re-enable afterwards

Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Daniel Miess <daniel.miess@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
index ab6d09c6fe348cc1900cbe83fcff6866890b77a6..76da59d8caaf545bc2815a6a464cc249fbbee7c0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.h
@@ -291,7 +291,11 @@
        type SYMCLKB_FE_SRC_SEL;\
        type SYMCLKC_FE_SRC_SEL;\
        type SYMCLKD_FE_SRC_SEL;\
-       type SYMCLKE_FE_SRC_SEL;
+       type SYMCLKE_FE_SRC_SEL;\
+       type DTBCLK_P0_GATE_DISABLE;\
+       type DTBCLK_P1_GATE_DISABLE;\
+       type DTBCLK_P2_GATE_DISABLE;\
+       type DTBCLK_P3_GATE_DISABLE;\
 
 struct dccg_shift {
        DCCG_REG_FIELD_LIST(uint8_t)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
index 479f3683c0b70eeeec8e77c5f1717c9533ca3f64..142efd390d8625a072eacd643f9f74e86384b8a5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.c
@@ -256,6 +256,21 @@ static void dccg35_set_dtbclk_dto(
        if (params->ref_dtbclk_khz && req_dtbclk_khz) {
                uint32_t modulo, phase;
 
+               switch (params->otg_inst) {
+               case 0:
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 1);
+                       break;
+               case 1:
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 1);
+                       break;
+               case 2:
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 1);
+                       break;
+               case 3:
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 1);
+                       break;
+               }
+
                // phase / modulo = dtbclk / dtbclk ref
                modulo = params->ref_dtbclk_khz * 1000;
                phase = req_dtbclk_khz * 1000;
@@ -280,6 +295,21 @@ static void dccg35_set_dtbclk_dto(
                REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
                                PIPE_DTO_SRC_SEL[params->otg_inst], 2);
        } else {
+               switch (params->otg_inst) {
+               case 0:
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, 0);
+                       break;
+               case 1:
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, 0);
+                       break;
+               case 2:
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, 0);
+                       break;
+               case 3:
+                       REG_UPDATE(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, 0);
+                       break;
+               }
+
                REG_UPDATE_2(OTG_PIXEL_RATE_CNTL[params->otg_inst],
                                DTBCLK_DTO_ENABLE[params->otg_inst], 0,
                                PIPE_DTO_SRC_SEL[params->otg_inst], params->is_hdmi ? 0 : 1);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h
index 423feb4c2f3f590341b1e722c33f8ce9a7a1e7ec..bde48bee0119b7a8c36da6ed9f1196f23ce68ecb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_dccg.h
@@ -34,6 +34,7 @@
 #define DCCG_REG_LIST_DCN35() \
        DCCG_REG_LIST_DCN314(),\
        SR(DPPCLK_CTRL),\
+       SR(DCCG_GATE_DISABLE_CNTL5),\
        SR(DCCG_GATE_DISABLE_CNTL6),\
        SR(DCCG_GLOBAL_FGCG_REP_CNTL),\
        SR(SYMCLKA_CLOCK_ENABLE),\
@@ -174,7 +175,11 @@
        DCCG_SF(SYMCLKB_CLOCK_ENABLE, SYMCLKB_FE_SRC_SEL, mask_sh),\
        DCCG_SF(SYMCLKC_CLOCK_ENABLE, SYMCLKC_FE_SRC_SEL, mask_sh),\
        DCCG_SF(SYMCLKD_CLOCK_ENABLE, SYMCLKD_FE_SRC_SEL, mask_sh),\
-       DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, mask_sh)
+       DCCG_SF(SYMCLKE_CLOCK_ENABLE, SYMCLKE_FE_SRC_SEL, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
+       DCCG_SF(DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
 
 struct dccg *dccg35_create(
                struct dc_context *ctx,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c
index 46f71ff08fd176a668732db37dac8c5ee0de16a5..0f60c40e1fc50a8117c3b3c0144ebaf4ba8d3625 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.c
@@ -332,13 +332,6 @@ void pg_cntl35_io_clk_pg_control(struct pg_cntl *pg_cntl, bool power_on)
        pg_cntl->pg_res_enable[PG_DCIO] = power_on;
 }
 
-void pg_cntl35_set_force_poweron_domain22(struct pg_cntl *pg_cntl, bool power_on)
-{
-       struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
-
-       REG_UPDATE(DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, power_on ? 1 : 0);
-}
-
 static bool pg_cntl35_plane_otg_status(struct pg_cntl *pg_cntl)
 {
        struct dcn_pg_cntl *pg_cntl_dcn = TO_DCN_PG_CNTL(pg_cntl);
@@ -508,8 +501,7 @@ static const struct pg_cntl_funcs pg_cntl35_funcs = {
        .mpcc_pg_control = pg_cntl35_mpcc_pg_control,
        .opp_pg_control = pg_cntl35_opp_pg_control,
        .optc_pg_control = pg_cntl35_optc_pg_control,
-       .dwb_pg_control = pg_cntl35_dwb_pg_control,
-       .set_force_poweron_domain22 = pg_cntl35_set_force_poweron_domain22
+       .dwb_pg_control = pg_cntl35_dwb_pg_control
 };
 
 struct pg_cntl *pg_cntl35_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h
index 069dae08e2224b2ccfafddd1ca0a467e2a1b2a92..3de240884d22fa23e662cfd68413e6590d20745e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_pg_cntl.h
@@ -183,7 +183,6 @@ void pg_cntl35_optc_pg_control(struct pg_cntl *pg_cntl,
        unsigned int optc_inst, bool power_on);
 void pg_cntl35_dwb_pg_control(struct pg_cntl *pg_cntl, bool power_on);
 void pg_cntl35_init_pg_status(struct pg_cntl *pg_cntl);
-void pg_cntl35_set_force_poweron_domain22(struct pg_cntl *pg_cntl, bool power_on);
 
 struct pg_cntl *pg_cntl35_create(
        struct dc_context *ctx,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h b/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
index 44b4df6469d1aa7a9e2be6af7e43eb5610b62852..52f045cfd52a99d425d77b361614326641a619b3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce/dce_hwseq.h
@@ -682,6 +682,7 @@ struct dce_hwseq_registers {
        uint32_t DCHUBBUB_ARB_HOSTVM_CNTL;
        uint32_t HPO_TOP_HW_CONTROL;
        uint32_t DMU_CLK_CNTL;
+       uint32_t DCCG_GATE_DISABLE_CNTL4;
        uint32_t DCCG_GATE_DISABLE_CNTL5;
 };
  /* set field name */
@@ -1199,7 +1200,19 @@ struct dce_hwseq_registers {
        type PHYBSYMCLK_ROOT_GATE_DISABLE;\
        type PHYCSYMCLK_ROOT_GATE_DISABLE;\
        type PHYDSYMCLK_ROOT_GATE_DISABLE;\
-       type PHYESYMCLK_ROOT_GATE_DISABLE;
+       type PHYESYMCLK_ROOT_GATE_DISABLE;\
+       type DTBCLK_P0_GATE_DISABLE;\
+       type DTBCLK_P1_GATE_DISABLE;\
+       type DTBCLK_P2_GATE_DISABLE;\
+       type DTBCLK_P3_GATE_DISABLE;\
+       type DPSTREAMCLK0_GATE_DISABLE;\
+       type DPSTREAMCLK1_GATE_DISABLE;\
+       type DPSTREAMCLK2_GATE_DISABLE;\
+       type DPSTREAMCLK3_GATE_DISABLE;\
+       type DPIASYMCLK0_GATE_DISABLE;\
+       type DPIASYMCLK1_GATE_DISABLE;\
+       type DPIASYMCLK2_GATE_DISABLE;\
+       type DPIASYMCLK3_GATE_DISABLE;
 
 struct dce_hwseq_shift {
        HWSEQ_REG_FIELD_LIST(uint8_t)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 5a8258287438e9fe27024173c55c0dd345f4ee9f..39260371beb9d47203a1f5538cc579e934d395c4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -145,17 +145,36 @@ void dcn35_init_hw(struct dc *dc)
                hws->funcs.bios_golden_init(dc);
        }
 
-       REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
-       REG_WRITE(DCCG_GATE_DISABLE_CNTL2,  0);
-
-       /* Disable gating for PHYASYMCLK. This will be enabled in dccg if needed */
-       REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, 1,
-                       PHYBSYMCLK_ROOT_GATE_DISABLE, 1,
-                       PHYCSYMCLK_ROOT_GATE_DISABLE, 1,
-                       PHYDSYMCLK_ROOT_GATE_DISABLE, 1,
-                       PHYESYMCLK_ROOT_GATE_DISABLE, 1);
+       if (!dc->debug.disable_clock_gate) {
+               REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
+               REG_WRITE(DCCG_GATE_DISABLE_CNTL2,  0);
+
+               /* Disable gating for PHYASYMCLK. This will be enabled in dccg if needed */
+               REG_UPDATE_5(DCCG_GATE_DISABLE_CNTL2, PHYASYMCLK_ROOT_GATE_DISABLE, 1,
+                               PHYBSYMCLK_ROOT_GATE_DISABLE, 1,
+                               PHYCSYMCLK_ROOT_GATE_DISABLE, 1,
+                               PHYDSYMCLK_ROOT_GATE_DISABLE, 1,
+                               PHYESYMCLK_ROOT_GATE_DISABLE, 1);
+
+               REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL4,
+                               DPIASYMCLK0_GATE_DISABLE, 0,
+                               DPIASYMCLK1_GATE_DISABLE, 0,
+                               DPIASYMCLK2_GATE_DISABLE, 0,
+                               DPIASYMCLK3_GATE_DISABLE, 0);
+
+               REG_WRITE(DCCG_GATE_DISABLE_CNTL5, 0xFFFFFFFF);
+               REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL5,
+                               DTBCLK_P0_GATE_DISABLE, 0,
+                               DTBCLK_P1_GATE_DISABLE, 0,
+                               DTBCLK_P2_GATE_DISABLE, 0,
+                               DTBCLK_P3_GATE_DISABLE, 0);
+               REG_UPDATE_4(DCCG_GATE_DISABLE_CNTL5,
+                               DPSTREAMCLK0_GATE_DISABLE, 0,
+                               DPSTREAMCLK1_GATE_DISABLE, 0,
+                               DPSTREAMCLK2_GATE_DISABLE, 0,
+                               DPSTREAMCLK3_GATE_DISABLE, 0);
 
-       REG_WRITE(DCCG_GATE_DISABLE_CNTL5, 0x1f7c3fcf);
+       }
 
        // Initialize the dccg
        if (res_pool->dccg->funcs->dccg_init)
@@ -332,9 +351,6 @@ void dcn35_init_hw(struct dc *dc)
        if (dc->res_pool->pg_cntl) {
                if (dc->res_pool->pg_cntl->funcs->init_pg_status)
                        dc->res_pool->pg_cntl->funcs->init_pg_status(dc->res_pool->pg_cntl);
-
-               if (dc->res_pool->pg_cntl->funcs->set_force_poweron_domain22)
-                       dc->res_pool->pg_cntl->funcs->set_force_poweron_domain22(dc->res_pool->pg_cntl, false);
        }
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h b/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h
index b9812afb886be16937ee1aae8d763600e7815e08..00ea3864dd4df4bbd5f8d4c15b6c4aaa4eb8e306 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/pg_cntl.h
@@ -47,8 +47,6 @@ struct pg_cntl_funcs {
        void (*optc_pg_control)(struct pg_cntl *pg_cntl, unsigned int optc_inst, bool power_on);
        void (*dwb_pg_control)(struct pg_cntl *pg_cntl, bool power_on);
        void (*init_pg_status)(struct pg_cntl *pg_cntl);
-
-       void (*set_force_poweron_domain22)(struct pg_cntl *pg_cntl, bool power_on);
 };
 
 #endif //__DC_PG_CNTL_H__

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index a4027bf053c5fd1e801066dce4cd5196f64c3794..5c935d94a95cda04dbbbd28c90b1ee83ee030b87 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -626,7 +626,19 @@ static struct dce_hwseq_registers hwseq_reg;
        HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYBSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
        HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYCSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
        HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYDSYMCLK_ROOT_GATE_DISABLE, mask_sh), \
-       HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh)
+       HWS_SF(, DCCG_GATE_DISABLE_CNTL2, PHYESYMCLK_ROOT_GATE_DISABLE, mask_sh),\
+       HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P0_GATE_DISABLE, mask_sh),\
+       HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P1_GATE_DISABLE, mask_sh),\
+       HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P2_GATE_DISABLE, mask_sh),\
+       HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DTBCLK_P3_GATE_DISABLE, mask_sh),\
+       HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK0_GATE_DISABLE, mask_sh),\
+       HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK1_GATE_DISABLE, mask_sh),\
+       HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK2_GATE_DISABLE, mask_sh),\
+       HWS_SF(, DCCG_GATE_DISABLE_CNTL5, DPSTREAMCLK3_GATE_DISABLE, mask_sh),\
+       HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK0_GATE_DISABLE, mask_sh),\
+       HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK1_GATE_DISABLE, mask_sh),\
+       HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK2_GATE_DISABLE, mask_sh),\
+       HWS_SF(, DCCG_GATE_DISABLE_CNTL4, DPIASYMCLK3_GATE_DISABLE, mask_sh)
 
 static const struct dce_hwseq_shift hwseq_shift = {
                HWSEQ_DCN35_MASK_SH_LIST(__SHIFT)
@@ -705,7 +717,7 @@ static const struct dc_debug_options debug_defaults_drv = {
        .disable_dcc = DCC_ENABLE,
        .disable_dpp_power_gate = true,
        .disable_hubp_power_gate = true,
-       .disable_clock_gate = true,
+       .disable_clock_gate = false,
        .disable_dsc_power_gate = true,
        .vsr_support = true,
        .performance_trace = false,

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
index 99aea102e3f741ea1702d75cd678001c7eefeb91..a51c4a9eaafe582084ce96c6ae150e7e19e0ec03 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.h
@@ -166,6 +166,7 @@ struct resource_pool *dcn35_create_resource_pool(
        SR(MMHUBBUB_MEM_PWR_CNTL), \
        SR(DCCG_GATE_DISABLE_CNTL), \
        SR(DCCG_GATE_DISABLE_CNTL2), \
+       SR(DCCG_GATE_DISABLE_CNTL4), \
        SR(DCCG_GATE_DISABLE_CNTL5), \
        SR(DCFCLK_CNTL),\
        SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \

diff --git a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h
index b646648792113088089a8a05e8355f9c8d0bb505..fca72e2ec92947d8f792c0e51974723c762fbae6 100644 (file)
--- a/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/dcn/dcn_3_5_0_sh_mask.h
@@ -6220,12 +6220,20 @@
 #define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x3
 #define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE__SHIFT                                         0x4
 #define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE__SHIFT                                        0x11
+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK0_GATE_DISABLE__SHIFT                                              0x17
+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK1_GATE_DISABLE__SHIFT                                              0x18
+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK2_GATE_DISABLE__SHIFT                                              0x19
+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK3_GATE_DISABLE__SHIFT                                              0x1a
 #define DCCG_GATE_DISABLE_CNTL4__PHYA_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000001L
 #define DCCG_GATE_DISABLE_CNTL4__PHYB_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000002L
 #define DCCG_GATE_DISABLE_CNTL4__PHYC_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000004L
 #define DCCG_GATE_DISABLE_CNTL4__PHYD_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000008L
 #define DCCG_GATE_DISABLE_CNTL4__PHYE_REFCLK_ROOT_GATE_DISABLE_MASK                                           0x00000010L
 #define DCCG_GATE_DISABLE_CNTL4__HDMICHARCLK0_ROOT_GATE_DISABLE_MASK                                          0x00020000L
+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK0_GATE_DISABLE_MASK                                                0x00800000L
+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK1_GATE_DISABLE_MASK                                                0x01000000L
+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK2_GATE_DISABLE_MASK                                                0x02000000L
+#define DCCG_GATE_DISABLE_CNTL4__DPIASYMCLK3_GATE_DISABLE_MASK                                                0x04000000L
 #define DPSTREAMCLK_CNTL__DPSTREAMCLK0_SRC_SEL__SHIFT                                                         0x0
 #define DPSTREAMCLK_CNTL__DPSTREAMCLK0_EN__SHIFT                                                              0x3
 #define DPSTREAMCLK_CNTL__DPSTREAMCLK1_SRC_SEL__SHIFT                                                         0x4