drm/amd/display: Refactor dcn31_panel_construct to avoid assert

[Why]
We want to avoid unnecessary asserts, one of which is hit in
dcn31_panel_construct when booting on a DCN32 asic that has an eDP
connector on a different DIG than A or B. The DIG-based mapping only
applies when edp0_on_dp1 is supported, therefore the check for valid
eng_id can be moved within the appropriate section of the if statement.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
index 5738989847268c10d529258e3346ecabe4502b7d..f9961a6446f3ef89690bf890865facff4a40be9d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn31/dcn31_panel_cntl.c
@@ -168,31 +168,33 @@ void dcn31_panel_cntl_construct(
        struct dcn31_panel_cntl *dcn31_panel_cntl,
        const struct panel_cntl_init_data *init_data)
 {
-       uint8_t pwrseq_inst = 0xF;
 
        dcn31_panel_cntl->base.funcs = &dcn31_link_panel_cntl_funcs;
        dcn31_panel_cntl->base.ctx = init_data->ctx;
        dcn31_panel_cntl->base.inst = init_data->inst;
 
-       switch (init_data->eng_id) {
-       case ENGINE_ID_DIGA:
-               pwrseq_inst = 0;
-               break;
-       case ENGINE_ID_DIGB:
-               pwrseq_inst = 1;
-               break;
-       default:
-               DC_LOG_WARNING("Unsupported pwrseq engine id: %d!\n", init_data->eng_id);
-               ASSERT(false);
-               break;
-       }
-
-       if (dcn31_panel_cntl->base.ctx->dc->config.support_edp0_on_dp1)
+       if (dcn31_panel_cntl->base.ctx->dc->config.support_edp0_on_dp1) {
                //If supported, power sequencer mapping shall follow the DIG instance
+               uint8_t pwrseq_inst = 0xF;
+
+               switch (init_data->eng_id) {
+               case ENGINE_ID_DIGA:
+                       pwrseq_inst = 0;
+                       break;
+               case ENGINE_ID_DIGB:
+                       pwrseq_inst = 1;
+                       break;
+               default:
+                       DC_LOG_WARNING("Unsupported pwrseq engine id: %d!\n", init_data->eng_id);
+                       ASSERT(false);
+                       break;
+               }
+
                dcn31_panel_cntl->base.pwrseq_inst = pwrseq_inst;
-       else
+       } else {
                /* If not supported, pwrseq will be assigned in order,
                 * so first pwrseq will be assigned to first panel instance (legacy behavior)
                 */
                dcn31_panel_cntl->base.pwrseq_inst = dcn31_panel_cntl->base.inst;
+       }
 }