drm/amd/display: Skip dmub memory flush when not needed
authorDillon Varone <dillon.varone@amd.com>
Fri, 4 Aug 2023 20:55:26 +0000 (16:55 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 30 Aug 2023 19:37:18 +0000 (15:37 -0400)
[WHY&HOW]
Readback is only necessary when loaded via CPU.

Reviewed-by: Chris Park <chris.park@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dmub/dmub_srv.h
drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c

index e7a50cbf254026cdb59773e35c628f50a3dd397f..7a892f7bc7b04006f6c2babd90751dc52a607cac 100644 (file)
@@ -142,6 +142,13 @@ enum dpia_notify_bw_alloc_status {
        DPIA_BW_ALLOC_CAPS_CHANGED
 };
 
+/* enum dmub_memory_access_type - memory access method */
+enum dmub_memory_access_type {
+       DMUB_MEMORY_ACCESS_DEFAULT,
+       DMUB_MEMORY_ACCESS_CPU = DMUB_MEMORY_ACCESS_DEFAULT,
+       DMUB_MEMORY_ACCESS_DMA
+};
+
 /**
  * struct dmub_region - dmub hw memory region
  * @base: base address for region, must be 256 byte aligned
@@ -264,6 +271,7 @@ struct dmub_srv_hw_params {
        bool dpia_hpd_int_enable_supported;
        bool disable_clock_gate;
        bool disallow_dispclk_dppclk_ds;
+       enum dmub_memory_access_type mem_access_type;
 };
 
 /**
index 53464c3e49c17c19b62f29c848f95d779bde4ce1..d7d142c5b06a9995a1f22e97c582357bc90e5a0b 100644 (file)
@@ -564,7 +564,8 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
                 * DMCUB when backdoor loading if the write from x86 hasn't been
                 * flushed yet. This only occurs in backdoor loading.
                 */
-               dmub_flush_buffer_mem(inst_fb);
+               if (params->mem_access_type == DMUB_MEMORY_ACCESS_CPU)
+                       dmub_flush_buffer_mem(inst_fb);
 
                if (params->fw_in_system_memory && dmub->hw_funcs.backdoor_load_zfb_mode)
                        dmub->hw_funcs.backdoor_load_zfb_mode(dmub, &cw0, &cw1);