MIPS: Convert R4600_V1_HIT_CACHEOP into a config option

Use a new config option to enable R4600 V1 cacheop hit workaround
and remove define from the different war.h files.

Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 595916e504a3e093c8b2f710d25e1352a4fade86..714cd81a779c7bf669ad3046ae67e5e4e3ea64fc 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -639,6 +639,7 @@ config SGI_IP22
        select SYS_SUPPORTS_64BIT_KERNEL
        select SYS_SUPPORTS_BIG_ENDIAN
        select WAR_R4600_V1_INDEX_ICACHEOP
+       select WAR_R4600_V1_HIT_CACHEOP
        select MIPS_L1_CACHE_SHIFT_7
        help
          This are the SGI Indy, Challenge S and Indigo2, as well as certain
@@ -2615,6 +2616,33 @@ config MIPS_CRC_SUPPORT
 config WAR_R4600_V1_INDEX_ICACHEOP
        bool
 
+# Pleasures of the R4600 V1.x.  Cite from the IDT R4600 V1.7 errata:
+#
+#  18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
+#      Hit_Invalidate_D and Create_Dirty_Excl_D should only be
+#      executed if there is no other dcache activity. If the dcache is
+#      accessed for another instruction immeidately preceding when these
+#      cache instructions are executing, it is possible that the dcache
+#      tag match outputs used by these cache instructions will be
+#      incorrect. These cache instructions should be preceded by at least
+#      four instructions that are not any kind of load or store
+#      instruction.
+#
+#      This is not allowed:    lw
+#                              nop
+#                              nop
+#                              nop
+#                              cache       Hit_Writeback_Invalidate_D
+#
+#      This is allowed:        lw
+#                              nop
+#                              nop
+#                              nop
+#                              nop
+#                              cache       Hit_Writeback_Invalidate_D
+config WAR_R4600_V1_HIT_CACHEOP
+       bool
+
 #
 # - Highmem only makes sense for the 32-bit kernel.
 # - The current highmem code will only work properly on physically indexed

diff --git a/arch/mips/include/asm/mach-cavium-octeon/war.h b/arch/mips/include/asm/mach-cavium-octeon/war.h
index 1e01e2f20086a70d981852c3f84073ea6495cfaa..915ce0352c20412bfcbca011556771d38c1f1d00 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/war.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/war.h
@@ -9,7 +9,6 @@
 #ifndef __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
 #define __ASM_MIPS_MACH_CAVIUM_OCTEON_WAR_H
 
-#define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0

diff --git a/arch/mips/include/asm/mach-generic/war.h b/arch/mips/include/asm/mach-generic/war.h
index 7614a1545d1c356459640af95037b733814e7222..44d14be2e1e599ec11426e9013bda2a9eec77e2c 100644 (file)
--- a/arch/mips/include/asm/mach-generic/war.h
+++ b/arch/mips/include/asm/mach-generic/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MACH_GENERIC_WAR_H
 #define __ASM_MACH_GENERIC_WAR_H
 
-#define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0

diff --git a/arch/mips/include/asm/mach-ip22/war.h b/arch/mips/include/asm/mach-ip22/war.h
index 3424c1e8a24f941094e9ece64f13a5ab465b9167..9154c54d428a98d4efec9863e43d693f5267479e 100644 (file)
--- a/arch/mips/include/asm/mach-ip22/war.h
+++ b/arch/mips/include/asm/mach-ip22/war.h
@@ -12,7 +12,6 @@
  * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
  */
 
-#define R4600_V1_HIT_CACHEOP_WAR       1
 #define R4600_V2_HIT_CACHEOP_WAR       1
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0

diff --git a/arch/mips/include/asm/mach-ip27/war.h b/arch/mips/include/asm/mach-ip27/war.h
index 5a91a7564fb90081c55338c50a2ff1a62480922e..e7c070c85b7cd56ee30de54790d44b0da28c74eb 100644 (file)
--- a/arch/mips/include/asm/mach-ip27/war.h
+++ b/arch/mips/include/asm/mach-ip27/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_IP27_WAR_H
 #define __ASM_MIPS_MACH_IP27_WAR_H
 
-#define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0

diff --git a/arch/mips/include/asm/mach-ip28/war.h b/arch/mips/include/asm/mach-ip28/war.h
index 0dc70d59909e8bb1351e7a9f1411af5fb62456b0..22d9f78bf552a594a8c527f29440882714bb5ac0 100644 (file)
--- a/arch/mips/include/asm/mach-ip28/war.h
+++ b/arch/mips/include/asm/mach-ip28/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_IP28_WAR_H
 #define __ASM_MIPS_MACH_IP28_WAR_H
 
-#define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0

diff --git a/arch/mips/include/asm/mach-ip30/war.h b/arch/mips/include/asm/mach-ip30/war.h
index 9f5c3305674c46d37165a3cc6e1de621e06ec16f..1400b030982eff08a53554f17814dc90b98f786b 100644 (file)
--- a/arch/mips/include/asm/mach-ip30/war.h
+++ b/arch/mips/include/asm/mach-ip30/war.h
@@ -5,7 +5,6 @@
 #ifndef __ASM_MIPS_MACH_IP30_WAR_H
 #define __ASM_MIPS_MACH_IP30_WAR_H
 
-#define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0

diff --git a/arch/mips/include/asm/mach-ip32/war.h b/arch/mips/include/asm/mach-ip32/war.h
index ac933b9119bb713d744abe419e095cb3c4904684..f91f4eddce8f0a846634dbc27db1d78bcaccdf4c 100644 (file)
--- a/arch/mips/include/asm/mach-ip32/war.h
+++ b/arch/mips/include/asm/mach-ip32/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_IP32_WAR_H
 #define __ASM_MIPS_MACH_IP32_WAR_H
 
-#define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0

diff --git a/arch/mips/include/asm/mach-malta/war.h b/arch/mips/include/asm/mach-malta/war.h
index 12c6393b6f31720b1bffc1ef89c7d34534317be6..a4d5d0926e81d808d959362547150df781541df2 100644 (file)
--- a/arch/mips/include/asm/mach-malta/war.h
+++ b/arch/mips/include/asm/mach-malta/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_MIPS_WAR_H
 #define __ASM_MIPS_MACH_MIPS_WAR_H
 
-#define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0

diff --git a/arch/mips/include/asm/mach-rc32434/war.h b/arch/mips/include/asm/mach-rc32434/war.h
index 62e04bea61b3233dc2e9a219d0a6aa5e5795fac6..82ce2d313eed82c0d6dab172e7ed51a5babe0510 100644 (file)
--- a/arch/mips/include/asm/mach-rc32434/war.h
+++ b/arch/mips/include/asm/mach-rc32434/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_MIPS_WAR_H
 #define __ASM_MIPS_MACH_MIPS_WAR_H
 
-#define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0

diff --git a/arch/mips/include/asm/mach-rm/war.h b/arch/mips/include/asm/mach-rm/war.h
index fe3c17f38650067b8c4dda70d0030e601a42e747..192ec3358ad0fd103967c416f6b6d00fdb52578e 100644 (file)
--- a/arch/mips/include/asm/mach-rm/war.h
+++ b/arch/mips/include/asm/mach-rm/war.h
@@ -12,7 +12,6 @@
  * The RM200C seems to have been shipped only with V2.0 R4600s
  */
 
-#define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       1
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0

diff --git a/arch/mips/include/asm/mach-sibyte/war.h b/arch/mips/include/asm/mach-sibyte/war.h
index d34f3c1d6741ee0b9e36a5f9670209682ec6bcaa..bf793d36c890e9a22497c2fd8ab1ab198208e1b3 100644 (file)
--- a/arch/mips/include/asm/mach-sibyte/war.h
+++ b/arch/mips/include/asm/mach-sibyte/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
 #define __ASM_MIPS_MACH_SIBYTE_WAR_H
 
-#define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
 
 #if defined(CONFIG_SB1_PASS_2_WORKAROUNDS)

diff --git a/arch/mips/include/asm/mach-tx49xx/war.h b/arch/mips/include/asm/mach-tx49xx/war.h
index eb0375da266a694f13100a3ae1ceaf36ddae1ed0..7da1a3ea54c704d4189b748067b762bdbf0fff89 100644 (file)
--- a/arch/mips/include/asm/mach-tx49xx/war.h
+++ b/arch/mips/include/asm/mach-tx49xx/war.h
@@ -8,7 +8,6 @@
 #ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
 #define __ASM_MIPS_MACH_TX49XX_WAR_H
 
-#define R4600_V1_HIT_CACHEOP_WAR       0
 #define R4600_V2_HIT_CACHEOP_WAR       0
 #define BCM1250_M3_WAR                 0
 #define SIBYTE_1956_WAR                        0

diff --git a/arch/mips/include/asm/war.h b/arch/mips/include/asm/war.h
index 3c8923692fca501ce7b3d12c41fd6276ed564879..d336a0e57093f2cba687383a89f9736a0e078ef5 100644 (file)
--- a/arch/mips/include/asm/war.h
+++ b/arch/mips/include/asm/war.h
@@ -72,37 +72,6 @@
 #define DADDI_WAR 0
 #endif
 
-/*
- * Pleasures of the R4600 V1.x.         Cite from the IDT R4600 V1.7 errata:
- *
- *  18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
- *     Hit_Invalidate_D and Create_Dirty_Excl_D should only be
- *     executed if there is no other dcache activity. If the dcache is
- *     accessed for another instruction immeidately preceding when these
- *     cache instructions are executing, it is possible that the dcache
- *     tag match outputs used by these cache instructions will be
- *     incorrect. These cache instructions should be preceded by at least
- *     four instructions that are not any kind of load or store
- *     instruction.
- *
- *     This is not allowed:    lw
- *                             nop
- *                             nop
- *                             nop
- *                             cache       Hit_Writeback_Invalidate_D
- *
- *     This is allowed:        lw
- *                             nop
- *                             nop
- *                             nop
- *                             nop
- *                             cache       Hit_Writeback_Invalidate_D
- */
-#ifndef R4600_V1_HIT_CACHEOP_WAR
-#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
-#endif
-
-
 /*
  * Writeback and invalidate the primary cache dcache before DMA.
  *

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index bf454da84a9bd5ab5c78ebc6329b918c8ce8a8f0..814a295a2df27657ef9218f29622d3e6950de5fb 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -132,7 +132,7 @@ struct bcache_ops *bcops = &no_sc_ops;
 do {                                                                   \
        if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x())            \
                *(volatile unsigned long *)CKSEG1;                      \
-       if (R4600_V1_HIT_CACHEOP_WAR)                                   \
+       if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP))                                        \
                __asm__ __volatile__("nop;nop;nop;nop");                \
 } while (0)
 

diff --git a/arch/mips/mm/page.c b/arch/mips/mm/page.c
index cd805b0055096626ed1c06fa5dc1172760e7da2f..ecad11f5c67ce08d47b620e1df58af2747442e86 100644 (file)
--- a/arch/mips/mm/page.c
+++ b/arch/mips/mm/page.c
@@ -250,7 +250,8 @@ static inline void build_clear_pref(u32 **buf, int off)
                if (cpu_has_cache_cdex_s) {
                        uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
                } else if (cpu_has_cache_cdex_p) {
-                       if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
+                       if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP) &&
+                           cpu_is_r4600_v1_x()) {
                                uasm_i_nop(buf);
                                uasm_i_nop(buf);
                                uasm_i_nop(buf);
@@ -402,7 +403,8 @@ static inline void build_copy_store_pref(u32 **buf, int off)
                if (cpu_has_cache_cdex_s) {
                        uasm_i_cache(buf, Create_Dirty_Excl_SD, off, A0);
                } else if (cpu_has_cache_cdex_p) {
-                       if (R4600_V1_HIT_CACHEOP_WAR && cpu_is_r4600_v1_x()) {
+                       if (IS_ENABLED(CONFIG_WAR_R4600_V1_HIT_CACHEOP) &&
+                           cpu_is_r4600_v1_x()) {
                                uasm_i_nop(buf);
                                uasm_i_nop(buf);
                                uasm_i_nop(buf);