arm64: dts: qcom: sm8350: add MDSS registers interconnect

Aside from the MDSS<->MEM interconnect, display devices have separate
interconnect for register access. Add this interconnect to the display
node.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-9-1149dd8399fe@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index 38ee0850c33582e690b9a575356d3b22151f489e..27f36e6366df1ae5f7dee8940d0d7f59b700ae23 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2490,8 +2490,12 @@
                        reg-names = "mdss";
 
                        interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>,
-                                       <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>;
-                       interconnect-names = "mdp0-mem", "mdp1-mem";
+                                       <&mmss_noc MASTER_MDP1 0 &mc_virt SLAVE_EBI1 0>,
+                                       <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+                                        &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+                       interconnect-names = "mdp0-mem",
+                                            "mdp1-mem",
+                                            "cpu-cfg";
 
                        power-domains = <&dispcc MDSS_GDSC>;
                        resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;