drm/i915/dpio: s/VLV_REF_DW13/VLV_REF_DW11/

Our VLV_REF_DW13 is actually VLV_REF_DW11. Rename it.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240422083457.23815-3-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c
index 49274d63271606bb92966dd60bfd3f1adfabb9aa..6693beafe9c01b1b32fbe437cbc77d9950183279 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dpll.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll.c
@@ -1880,19 +1880,19 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv,
        reg_val |= 0x00000030;
        vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
 
-       reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13);
+       reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
        reg_val &= 0x00ffffff;
        reg_val |= 0x8c000000;
-       vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val);
+       vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
 
        reg_val = vlv_dpio_read(dev_priv, phy, VLV_PLL_DW9(1));
        reg_val &= 0xffffff00;
        vlv_dpio_write(dev_priv, phy, VLV_PLL_DW9(1), reg_val);
 
-       reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW13);
+       reg_val = vlv_dpio_read(dev_priv, phy, VLV_REF_DW11);
        reg_val &= 0x00ffffff;
        reg_val |= 0xb0000000;
-       vlv_dpio_write(dev_priv, phy, VLV_REF_DW13, reg_val);
+       vlv_dpio_write(dev_priv, phy, VLV_REF_DW11, reg_val);
 }
 
 static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index beed2b97d4b279dceb60f765c8769b422ed987e7..c6840e15d2450c7c28a2944aa1312c439c3bb3d3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -246,8 +246,8 @@
 #define _VLV_PLL_DW11_CH1              0x806c
 #define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
 
-/* Spec for ref block start counts at DW10 */
-#define VLV_REF_DW13                   0x80ac
+/* Spec for ref block start counts at DW8 */
+#define VLV_REF_DW11                   0x80ac
 
 #define VLV_CMN_DW0                    0x8100