riscv: dts: sophgo: Use common "interrupt-parent" for all peripherals for sg2042

As all peripherals of sg2042 share the same "interrupt-parent",
there is no need to use peripherals specific "interrupt-parent".
Define "interrupt-parent" in the SoC level.

Reviewed-by: Chen Wang <unicorn_wang@outlook.com>
Tested-by: Chen Wang <unicorn_wang@outlook.com>
Link: https://lore.kernel.org/r/IA1PR20MB49531F6DFD2F116207C1397DBBB72@IA1PR20MB4953.namprd20.prod.outlook.com
Signed-off-by: Inochi Amaoto <inochiama@outlook.com>
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>

diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
index 34c802bd3f9b8e51ce13841bf5e715421d1f338d..c61d8061119dc732ff85beebed5f4b8dc41bd920 100644 (file)
--- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi
@@ -44,6 +44,7 @@
                compatible = "simple-bus";
                #address-cells = <2>;
                #size-cells = <2>;
+               interrupt-parent = <&intc>;
                ranges;
 
                pllclk: clock-controller@70300100c0 {
@@ -388,7 +389,6 @@
                uart0: serial@7040000000 {
                        compatible = "snps,dw-apb-uart";
                        reg = <0x00000070 0x40000000 0x00000000 0x00001000>;
-                       interrupt-parent = <&intc>;
                        interrupts = <112 IRQ_TYPE_LEVEL_HIGH>;
                        clock-frequency = <500000000>;
                        clocks = <&clkgen GATE_CLK_UART_500M>,