power: supply: smb347-charger: Add missing pin control activation
authorDmitry Osipenko <digetx@gmail.com>
Sat, 31 Jul 2021 17:38:38 +0000 (20:38 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 15 Sep 2021 07:50:25 +0000 (09:50 +0200)
[ Upstream commit efe2175478d5237949e33c84d9a722fc084b218c ]

Pin control needs to be activated by setting the enable bit, otherwise
hardware rejects all pin changes. Previously this stayed unnoticed on
Nexus 7 because pin control was enabled by default after rebooting from
downstream kernel, which uses driver that enables the bit and charger
registers are non-volatile until power supply (battery) is disconnected.
Configure the pin control enable bit. This fixes the potentially
never-enabled charging on devices that use pin control.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
drivers/power/supply/smb347-charger.c

index 8cfbd8d6b478681f82a67d634c039707976f12a3..912e2184f918c94352a60cf1393d4594cf9d517f 100644 (file)
@@ -56,6 +56,7 @@
 #define CFG_PIN_EN_CTRL_ACTIVE_LOW             0x60
 #define CFG_PIN_EN_APSD_IRQ                    BIT(1)
 #define CFG_PIN_EN_CHARGER_ERROR               BIT(2)
+#define CFG_PIN_EN_CTRL                                BIT(4)
 #define CFG_THERM                              0x07
 #define CFG_THERM_SOFT_HOT_COMPENSATION_MASK   0x03
 #define CFG_THERM_SOFT_HOT_COMPENSATION_SHIFT  0
@@ -725,6 +726,15 @@ static int smb347_hw_init(struct smb347_charger *smb)
        if (ret < 0)
                goto fail;
 
+       /* Activate pin control, making it writable. */
+       switch (smb->enable_control) {
+       case SMB3XX_CHG_ENABLE_PIN_ACTIVE_LOW:
+       case SMB3XX_CHG_ENABLE_PIN_ACTIVE_HIGH:
+               ret = regmap_set_bits(smb->regmap, CFG_PIN, CFG_PIN_EN_CTRL);
+               if (ret < 0)
+                       goto fail;
+       }
+
        /*
         * Make the charging functionality controllable by a write to the
         * command register unless pin control is specified in the platform