drm/amdgpu/gfx9.4.3: add ring reset callback

Add ring reset callback for compute.

Acked-by: Vitaly Prosyak <vitaly.prosyak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index 7b4ae197eb49bd03d80f6b0c07a7b242c1807b84..f1c73bc1bd95e319d078cb9ae1f36f18ba1ed17b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -3426,6 +3426,43 @@ static void gfx_v9_4_3_emit_wave_limit(struct amdgpu_ring *ring, bool enable)
        }
 }
 
+static int gfx_v9_4_3_reset_kcq(struct amdgpu_ring *ring,
+                               unsigned int vmid)
+{
+       struct amdgpu_device *adev = ring->adev;
+       struct amdgpu_kiq *kiq = &adev->gfx.kiq[ring->xcc_id];
+       struct amdgpu_ring *kiq_ring = &kiq->ring;
+       unsigned long flags;
+       int r;
+
+       if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
+               return -EINVAL;
+
+       spin_lock_irqsave(&kiq->ring_lock, flags);
+
+       if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
+               spin_unlock_irqrestore(&kiq->ring_lock, flags);
+               return -ENOMEM;
+       }
+
+       kiq->pmf->kiq_unmap_queues(kiq_ring, ring, RESET_QUEUES,
+                                  0, 0);
+       amdgpu_ring_commit(kiq_ring);
+
+       spin_unlock_irqrestore(&kiq->ring_lock, flags);
+
+       r = amdgpu_ring_test_ring(kiq_ring);
+       if (r)
+               return r;
+
+       /* reset the ring */
+       ring->wptr = 0;
+       *ring->wptr_cpu_addr = 0;
+       amdgpu_ring_clear_ring(ring);
+
+       return amdgpu_ring_test_ring(ring);
+}
+
 enum amdgpu_gfx_cp_ras_mem_id {
        AMDGPU_GFX_CP_MEM1 = 1,
        AMDGPU_GFX_CP_MEM2,
@@ -4536,6 +4573,7 @@ static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_compute = {
        .soft_recovery = gfx_v9_4_3_ring_soft_recovery,
        .emit_mem_sync = gfx_v9_4_3_emit_mem_sync,
        .emit_wave_limit = gfx_v9_4_3_emit_wave_limit,
+       .reset = gfx_v9_4_3_reset_kcq,
 };
 
 static const struct amdgpu_ring_funcs gfx_v9_4_3_ring_funcs_kiq = {