staging: mt7621-pci: Add spaces around '<<'

Add spaces around '<<' to fix checkpatch issue.
CHECK: spaces preferred around that '<<' (ctx:VxV)

Signed-off-by: Mamta Shukla <mamtashukla555@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 780ba56a3d61e13630015cd9d4d000fa4f6a3ff2..31b448d6449a6b32e91825ebc3c1e1fdb3eb19fc 100644 (file)
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -474,12 +474,12 @@ static int mt7621_pci_probe(struct platform_device *pdev)
 
        ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST | RALINK_PCIE1_RST | RALINK_PCIE2_RST);
 
-       *(unsigned int *)(0xbe000060) &= ~(0x3<<10 | 0x3<<3);
-       *(unsigned int *)(0xbe000060) |= 0x1<<10 | 0x1<<3;
+       *(unsigned int *)(0xbe000060) &= ~(0x3 << 10 | 0x3 << 3);
+       *(unsigned int *)(0xbe000060) |= 0x1 << 10 | 0x1 << 3;
        mdelay(100);
-       *(unsigned int *)(0xbe000600) |= 0x1<<19 | 0x1<<8 | 0x1<<7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
+       *(unsigned int *)(0xbe000600) |= 0x1 << 19 | 0x1 << 8 | 0x1 << 7; // use GPIO19/GPIO8/GPIO7 (PERST_N/UART_RXD3/UART_TXD3)
        mdelay(100);
-       *(unsigned int *)(0xbe000620) &= ~(0x1<<19 | 0x1<<8 | 0x1<<7);          // clear DATA
+       *(unsigned int *)(0xbe000620) &= ~(0x1 << 19 | 0x1 << 8 | 0x1 << 7);            // clear DATA
 
        mdelay(100);
 
@@ -510,18 +510,18 @@ static int mt7621_pci_probe(struct platform_device *pdev)
        rt_sysc_m32(RALINK_PCIE_RST, 0, RALINK_RSTCTRL);
 
        /* Use GPIO control instead of PERST_N */
-       *(unsigned int *)(0xbe000620) |= 0x1<<19 | 0x1<<8 | 0x1<<7;             // set DATA
+       *(unsigned int *)(0xbe000620) |= 0x1 << 19 | 0x1 << 8 | 0x1 << 7;               // set DATA
        mdelay(1000);
 
        if ((pcie_read(pcie, RT6855_PCIE0_OFFSET + RALINK_PCI_STATUS) & 0x1) == 0) {
                printk("PCIE0 no card, disable it(RST&CLK)\n");
                ASSERT_SYSRST_PCIE(RALINK_PCIE0_RST);
                rt_sysc_m32(RALINK_PCIE0_CLK_EN, 0, RALINK_CLKCFG1);
-               pcie_link_status &= ~(1<<0);
+               pcie_link_status &= ~(1 << 0);
        } else {
-               pcie_link_status |= 1<<0;
+               pcie_link_status |= 1 << 0;
                val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
-               val |= (1<<20); // enable pcie1 interrupt
+               val |= (1 << 20); // enable pcie1 interrupt
                pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
        }
 
@@ -529,11 +529,11 @@ static int mt7621_pci_probe(struct platform_device *pdev)
                printk("PCIE1 no card, disable it(RST&CLK)\n");
                ASSERT_SYSRST_PCIE(RALINK_PCIE1_RST);
                rt_sysc_m32(RALINK_PCIE1_CLK_EN, 0, RALINK_CLKCFG1);
-               pcie_link_status &= ~(1<<1);
+               pcie_link_status &= ~(1 << 1);
        } else {
-               pcie_link_status |= 1<<1;
+               pcie_link_status |= 1 << 1;
                val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
-               val |= (1<<21); // enable pcie1 interrupt
+               val |= (1 << 21); // enable pcie1 interrupt
                pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
        }
 
@@ -541,11 +541,11 @@ static int mt7621_pci_probe(struct platform_device *pdev)
                printk("PCIE2 no card, disable it(RST&CLK)\n");
                ASSERT_SYSRST_PCIE(RALINK_PCIE2_RST);
                rt_sysc_m32(RALINK_PCIE2_CLK_EN, 0, RALINK_CLKCFG1);
-               pcie_link_status &= ~(1<<2);
+               pcie_link_status &= ~(1 << 2);
        } else {
-               pcie_link_status |= 1<<2;
+               pcie_link_status |= 1 << 2;
                val = pcie_read(pcie, RALINK_PCI_PCIMSK_ADDR);
-               val |= (1<<22); // enable pcie2 interrupt
+               val |= (1 << 22); // enable pcie2 interrupt
                pcie_write(pcie, val, RALINK_PCI_PCIMSK_ADDR);
        }
 
@@ -646,8 +646,8 @@ pcie(2/1/0) link status     pcie2_num       pcie1_num       pcie0_num
                val = read_config(pcie, 2, 0x4);
                write_config(pcie, 2, 0x4, val | 0x4);
                val = read_config(pcie, 2, 0x70c);
-               val &= ~(0xff)<<8;
-               val |= 0x50<<8;
+               val &= ~(0xff) << 8;
+               val |= 0x50 << 8;
                write_config(pcie, 2, 0x70c, val);
        case 3:
        case 5:
@@ -655,15 +655,15 @@ pcie(2/1/0) link status   pcie2_num       pcie1_num       pcie0_num
                val = read_config(pcie, 1, 0x4);
                write_config(pcie, 1, 0x4, val | 0x4);
                val = read_config(pcie, 1, 0x70c);
-               val &= ~(0xff)<<8;
-               val |= 0x50<<8;
+               val &= ~(0xff) << 8;
+               val |= 0x50 << 8;
                write_config(pcie, 1, 0x70c, val);
        default:
                val = read_config(pcie, 0, 0x4);
                write_config(pcie, 0, 0x4, val | 0x4); //bus master enable
                val = read_config(pcie, 0, 0x70c);
-               val &= ~(0xff)<<8;
-               val |= 0x50<<8;
+               val &= ~(0xff) << 8;
+               val |= 0x50 << 8;
                write_config(pcie, 0, 0x70c, val);
        }