drm/amdgpu: disable workload profile switching when OD is enabled
authorAlex Deucher <alexander.deucher@amd.com>
Tue, 27 May 2025 14:13:31 +0000 (10:13 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 3 Jun 2025 19:04:24 +0000 (15:04 -0400)
Users have reported that they have to reduce the level of undervolting
to acheive stability when dynamic workload profiles are enabled on
GC 10.3.x. Disable dynamic workload profiles if the user has enabled
OD.

Fixes: b9467983b774 ("drm/amdgpu: add dynamic workload profile switching for gfx10")
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4262
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.15.x
drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c
drivers/gpu/drm/amd/pm/amdgpu_dpm.c
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h

index 1db1e6ec0184fcd93dd8f2f8f9a365d08e91d0f6..c5646af055abcbce1db22aa61295d9a0f5e06165 100644 (file)
@@ -2228,6 +2228,9 @@ void amdgpu_gfx_profile_ring_begin_use(struct amdgpu_ring *ring)
        enum PP_SMC_POWER_PROFILE profile;
        int r;
 
+       if (amdgpu_dpm_is_overdrive_enabled(adev))
+               return;
+
        if (adev->gfx.num_gfx_rings)
                profile = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
        else
@@ -2258,6 +2261,11 @@ void amdgpu_gfx_profile_ring_begin_use(struct amdgpu_ring *ring)
 
 void amdgpu_gfx_profile_ring_end_use(struct amdgpu_ring *ring)
 {
+       struct amdgpu_device *adev = ring->adev;
+
+       if (amdgpu_dpm_is_overdrive_enabled(adev))
+               return;
+
        atomic_dec(&ring->adev->gfx.total_submission_cnt);
 
        schedule_delayed_work(&ring->adev->gfx.idle_work, GFX_PROFILE_IDLE_TIMEOUT);
index d98c95d1ed838e26d839da07440f25a742306f2c..5c1cbdc122d24a2134cab411e5adb2b33ee26a93 100644 (file)
@@ -1697,6 +1697,28 @@ int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev)
        }
 }
 
+int amdgpu_dpm_is_overdrive_enabled(struct amdgpu_device *adev)
+{
+       if (is_support_sw_smu(adev)) {
+               struct smu_context *smu = adev->powerplay.pp_handle;
+
+               return smu->od_enabled;
+       } else {
+               struct pp_hwmgr *hwmgr;
+
+               /*
+                * dpm on some legacy asics don't carry od_enabled member
+                * as its pp_handle is casted directly from adev.
+                */
+               if (amdgpu_dpm_is_legacy_dpm(adev))
+                       return false;
+
+               hwmgr = (struct pp_hwmgr *)adev->powerplay.pp_handle;
+
+               return hwmgr->od_enabled;
+       }
+}
+
 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev,
                            const char *buf,
                            size_t size)
index c0f9ecb97fcc912862f1e15d4c95c257c2b7cc77..768317ee1486b98f6d06332880167f79bd8e529a 100644 (file)
@@ -563,6 +563,7 @@ int amdgpu_dpm_get_smu_prv_buf_details(struct amdgpu_device *adev,
                                       void **addr,
                                       size_t *size);
 int amdgpu_dpm_is_overdrive_supported(struct amdgpu_device *adev);
+int amdgpu_dpm_is_overdrive_enabled(struct amdgpu_device *adev);
 int amdgpu_dpm_set_pp_table(struct amdgpu_device *adev,
                            const char *buf,
                            size_t size);