drm/amdgpu: add userq firmware version checks
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 28 Feb 2025 19:50:11 +0000 (14:50 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 8 Apr 2025 20:48:21 +0000 (16:48 -0400)
Currently disabled until the firmwares are officially
released.

Reviewed-by: Prike Liang <Prike.Liang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c

index 80af0b92d6b11421a335a74228575222835c60ec..f98c9c8253f8774870b193ba4fff3525a48f2462 100644 (file)
@@ -1623,8 +1623,11 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
                adev->gfx.mec.num_pipe_per_mec = 4;
                adev->gfx.mec.num_queue_per_pipe = 4;
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
-               adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
-               adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
+               /* add firmware version checks here */
+               if (0) {
+                       adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
+                       adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
+               }
 #endif
                break;
        case IP_VERSION(11, 0, 1):
@@ -1640,8 +1643,11 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
                adev->gfx.mec.num_pipe_per_mec = 4;
                adev->gfx.mec.num_queue_per_pipe = 4;
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
-               adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
-               adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
+               /* add firmware version checks here */
+               if (0) {
+                       adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
+                       adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
+               }
 #endif
                break;
        default:
index 0e95c1cfeca639af81942c77b1ab59b4f5a1f878..58f17d95b2f5ba428f97c82621620aa1088cd9ef 100644 (file)
@@ -1420,8 +1420,11 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
                adev->gfx.mec.num_pipe_per_mec = 2;
                adev->gfx.mec.num_queue_per_pipe = 4;
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
-               adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
-               adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
+               /* add firmware version checks here */
+               if (0) {
+                       adev->userq_funcs[AMDGPU_HW_IP_GFX] = &userq_mes_funcs;
+                       adev->userq_funcs[AMDGPU_HW_IP_COMPUTE] = &userq_mes_funcs;
+               }
 #endif
                break;
        default:
index 9bc3c7a35d185cf79ead72629b851ebec9f485d8..3aa4fec4d9e4ac9bd5451462c8d744a01bdc7db8 100644 (file)
@@ -1381,7 +1381,9 @@ static int sdma_v6_0_sw_init(struct amdgpu_ip_block *ip_block)
                DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
 
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
-       adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
+       /* add firmware version checks here */
+       if (0)
+               adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
 #endif
        r = amdgpu_sdma_sysfs_reset_mask_init(adev);
        if (r)
index 3514089acd942c405d6d50ae2e5fed791666e757..8e3aa4536e5a61dd788de97c32a9079f01614cf1 100644 (file)
@@ -1383,7 +1383,9 @@ static int sdma_v7_0_sw_init(struct amdgpu_ip_block *ip_block)
                DRM_ERROR("Failed to allocated memory for SDMA IP Dump\n");
 
 #ifdef CONFIG_DRM_AMDGPU_NAVI3X_USERQ
-       adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
+       /* add firmware version checks here */
+       if (0)
+               adev->userq_funcs[AMDGPU_HW_IP_DMA] = &userq_mes_funcs;
 #endif