arm64: dts: qcom: sdm845: Add first PCIe controller and PHY

Add the GEN2 PCIe controller and PHY found on SDM845.

Tested-by: Julien Massot <jmassot@softbankrobotics.com>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20191107002247.1127689-2-bjorn.andersson@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index d42302b8889b6b18db2903d3a6c5cb8bd8b1ac85..9ac2e85d81819c62553f1537edc71f36aad8d1e5 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -1364,6 +1364,110 @@
                        interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
                };
 
+               pcie0: pci@1c00000 {
+                       compatible = "qcom,pcie-sdm845", "snps,dw-pcie";
+                       reg = <0 0x01c00000 0 0x2000>,
+                             <0 0x60000000 0 0xf1d>,
+                             <0 0x60000f20 0 0xa8>,
+                             <0 0x60100000 0 0x100000>;
+                       reg-names = "parf", "dbi", "elbi", "config";
+                       device_type = "pci";
+                       linux,pci-domain = <0>;
+                       bus-range = <0x00 0xff>;
+                       num-lanes = <1>;
+
+                       #address-cells = <3>;
+                       #size-cells = <2>;
+
+                       ranges = <0x01000000 0x0 0x60200000 0 0x60200000 0x0 0x100000>,
+                                <0x02000000 0x0 0x60300000 0 0x60300000 0x0 0xd00000>;
+
+                       interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "msi";
+                       #interrupt-cells = <1>;
+                       interrupt-map-mask = <0 0 0 0x7>;
+                       interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
+                                       <0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
+                                       <0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
+                                       <0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
+
+                       clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
+                                <&gcc GCC_PCIE_0_AUX_CLK>,
+                                <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                                <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
+                                <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
+                                <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
+                                <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
+                       clock-names = "pipe",
+                                     "aux",
+                                     "cfg",
+                                     "bus_master",
+                                     "bus_slave",
+                                     "slave_q2a",
+                                     "tbu";
+
+                       iommus = <&apps_smmu 0x1c10 0xf>;
+                       iommu-map = <0x0   &apps_smmu 0x1c10 0x1>,
+                                   <0x100 &apps_smmu 0x1c11 0x1>,
+                                   <0x200 &apps_smmu 0x1c12 0x1>,
+                                   <0x300 &apps_smmu 0x1c13 0x1>,
+                                   <0x400 &apps_smmu 0x1c14 0x1>,
+                                   <0x500 &apps_smmu 0x1c15 0x1>,
+                                   <0x600 &apps_smmu 0x1c16 0x1>,
+                                   <0x700 &apps_smmu 0x1c17 0x1>,
+                                   <0x800 &apps_smmu 0x1c18 0x1>,
+                                   <0x900 &apps_smmu 0x1c19 0x1>,
+                                   <0xa00 &apps_smmu 0x1c1a 0x1>,
+                                   <0xb00 &apps_smmu 0x1c1b 0x1>,
+                                   <0xc00 &apps_smmu 0x1c1c 0x1>,
+                                   <0xd00 &apps_smmu 0x1c1d 0x1>,
+                                   <0xe00 &apps_smmu 0x1c1e 0x1>,
+                                   <0xf00 &apps_smmu 0x1c1f 0x1>;
+
+                       resets = <&gcc GCC_PCIE_0_BCR>;
+                       reset-names = "pci";
+
+                       power-domains = <&gcc PCIE_0_GDSC>;
+
+                       phys = <&pcie0_lane>;
+                       phy-names = "pciephy";
+
+                       status = "disabled";
+               };
+
+               pcie0_phy: phy@1c06000 {
+                       compatible = "qcom,sdm845-qmp-pcie-phy";
+                       reg = <0 0x01c06000 0 0x18c>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+                       clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
+                                <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
+                                <&gcc GCC_PCIE_0_CLKREF_CLK>,
+                                <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
+                       clock-names = "aux", "cfg_ahb", "ref", "refgen";
+
+                       resets = <&gcc GCC_PCIE_0_PHY_BCR>;
+                       reset-names = "phy";
+
+                       assigned-clocks = <&gcc GCC_PCIE_PHY_REFGEN_CLK>;
+                       assigned-clock-rates = <100000000>;
+
+                       status = "disabled";
+
+                       pcie0_lane: lanes@1c06200 {
+                               reg = <0 0x01c06200 0 0x128>,
+                                     <0 0x01c06400 0 0x1fc>,
+                                     <0 0x01c06800 0 0x218>,
+                                     <0 0x01c06600 0 0x70>;
+                               clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
+                               clock-names = "pipe0";
+
+                               #phy-cells = <0>;
+                               clock-output-names = "pcie_0_pipe_clk";
+                       };
+               };
+
                ufs_mem_hc: ufshc@1d84000 {
                        compatible = "qcom,sdm845-ufshc", "qcom,ufshc",
                                     "jedec,ufs-2.0";