arm64: dts: qcom: sm6350: Add UFS nodes

Add the necessary nodes for UFS and its PHY.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220321133318.99406-6-luca.weiss@fairphone.com

diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 81db25952cf1b4cf2223b25e46d35a94e9185df8..f6fb97d5ca92d548ca7f9e9530aaa45ccb418253 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -633,6 +633,83 @@
 
                };
 
+               ufs_mem_hc: ufs@1d84000 {
+                       compatible = "qcom,sm6350-ufshc", "qcom,ufshc",
+                                    "jedec,ufs-2.0";
+                       reg = <0 0x01d84000 0 0x3000>,
+                             <0 0x01d90000 0 0x8000>;
+                       reg-names = "std", "ice";
+                       interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
+                       phys = <&ufs_mem_phy_lanes>;
+                       phy-names = "ufsphy";
+                       lanes-per-direction = <2>;
+                       #reset-cells = <1>;
+                       resets = <&gcc GCC_UFS_PHY_BCR>;
+                       reset-names = "rst";
+
+                       power-domains = <&gcc UFS_PHY_GDSC>;
+
+                       iommus = <&apps_smmu 0x80 0x0>;
+
+                       clock-names = "core_clk",
+                                     "bus_aggr_clk",
+                                     "iface_clk",
+                                     "core_clk_unipro",
+                                     "ref_clk",
+                                     "tx_lane0_sync_clk",
+                                     "rx_lane0_sync_clk",
+                                     "rx_lane1_sync_clk",
+                                     "ice_core_clk";
+                       clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
+                                <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
+                                <&gcc GCC_UFS_PHY_AHB_CLK>,
+                                <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
+                                <&rpmhcc RPMH_QLINK_CLK>,
+                                <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
+                                <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
+                                <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>,
+                                <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+                       freq-table-hz =
+                               <50000000 200000000>,
+                               <0 0>,
+                               <0 0>,
+                               <37500000 150000000>,
+                               <75000000 300000000>,
+                               <0 0>,
+                               <0 0>,
+                               <0 0>,
+                               <0 0>;
+
+                       status = "disabled";
+               };
+
+               ufs_mem_phy: phy@1d87000 {
+                       compatible = "qcom,sm6350-qmp-ufs-phy";
+                       reg = <0 0x01d87000 0 0x18c>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+
+                       clock-names = "ref",
+                                     "ref_aux";
+                       clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
+                                <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
+
+                       resets = <&ufs_mem_hc 0>;
+                       reset-names = "ufsphy";
+
+                       status = "disabled";
+
+                       ufs_mem_phy_lanes: phy@1d87400 {
+                               reg = <0 0x01d87400 0 0x128>,
+                                     <0 0x01d87600 0 0x1fc>,
+                                     <0 0x01d87c00 0 0x1dc>,
+                                     <0 0x01d87800 0 0x128>,
+                                     <0 0x01d87a00 0 0x1fc>;
+                               #phy-cells = <0>;
+                       };
+               };
+
                tcsr_mutex: hwlock@1f40000 {
                        compatible = "qcom,tcsr-mutex";
                        reg = <0x0 0x01f40000 0x0 0x40000>;