drm/amd/pm:add UMD Pstate clock settings for smu_v13_0_7

add UMD Pstate clock settings for smu_v13_0_7

Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
index 9e5ea20f2342f5dd9d98d4da599bf9b1cd06ec3c..4c7154f9b80b1edacfd7ff3870f1b08e8df1c0b9 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
@@ -1226,6 +1226,57 @@ static ssize_t smu_v13_0_7_get_gpu_metrics(struct smu_context *smu,
        return sizeof(struct gpu_metrics_v1_3);
 }
 
+static int smu_v13_0_7_populate_umd_state_clk(struct smu_context *smu)
+{
+       struct smu_13_0_dpm_context *dpm_context =
+                               smu->smu_dpm.dpm_context;
+       struct smu_13_0_dpm_table *gfx_table =
+                               &dpm_context->dpm_tables.gfx_table;
+       struct smu_13_0_dpm_table *mem_table =
+                               &dpm_context->dpm_tables.uclk_table;
+       struct smu_13_0_dpm_table *soc_table =
+                               &dpm_context->dpm_tables.soc_table;
+       struct smu_13_0_dpm_table *vclk_table =
+                               &dpm_context->dpm_tables.vclk_table;
+       struct smu_13_0_dpm_table *dclk_table =
+                               &dpm_context->dpm_tables.dclk_table;
+       struct smu_13_0_dpm_table *fclk_table =
+                               &dpm_context->dpm_tables.fclk_table;
+       struct smu_umd_pstate_table *pstate_table =
+                               &smu->pstate_table;
+
+       pstate_table->gfxclk_pstate.min = gfx_table->min;
+       pstate_table->gfxclk_pstate.peak = gfx_table->max;
+
+       pstate_table->uclk_pstate.min = mem_table->min;
+       pstate_table->uclk_pstate.peak = mem_table->max;
+
+       pstate_table->socclk_pstate.min = soc_table->min;
+       pstate_table->socclk_pstate.peak = soc_table->max;
+
+       pstate_table->vclk_pstate.min = vclk_table->min;
+       pstate_table->vclk_pstate.peak = vclk_table->max;
+
+       pstate_table->dclk_pstate.min = dclk_table->min;
+       pstate_table->dclk_pstate.peak = dclk_table->max;
+
+       pstate_table->fclk_pstate.min = fclk_table->min;
+       pstate_table->fclk_pstate.peak = fclk_table->max;
+
+       /*
+        * For now, just use the mininum clock frequency.
+        * TODO: update them when the real pstate settings available
+        */
+       pstate_table->gfxclk_pstate.standard = gfx_table->min;
+       pstate_table->uclk_pstate.standard = mem_table->min;
+       pstate_table->socclk_pstate.standard = soc_table->min;
+       pstate_table->vclk_pstate.standard = vclk_table->min;
+       pstate_table->dclk_pstate.standard = dclk_table->min;
+       pstate_table->fclk_pstate.standard = fclk_table->min;
+
+       return 0;
+}
+
 static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
        .get_allowed_feature_mask = smu_v13_0_7_get_allowed_feature_mask,
        .set_default_dpm_table = smu_v13_0_7_set_default_dpm_table,
@@ -1246,6 +1297,7 @@ static const struct pptable_funcs smu_v13_0_7_ppt_funcs = {
        .dpm_set_vcn_enable = smu_v13_0_set_vcn_enable,
        .dpm_set_jpeg_enable = smu_v13_0_set_jpeg_enable,
        .init_pptable_microcode = smu_v13_0_init_pptable_microcode,
+       .populate_umd_state_clk = smu_v13_0_7_populate_umd_state_clk,
        .get_dpm_ultimate_freq = smu_v13_0_get_dpm_ultimate_freq,
        .get_vbios_bootup_values = smu_v13_0_get_vbios_bootup_values,
        .read_sensor = smu_v13_0_7_read_sensor,