arm64: dts: imx8: add mu5/6 node

Add mu5/6 for i.MX8QXP/QM, these two mu will be used for
communicating with general purpose Cortex-M4 cores.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
index ee4e585a9c391aff4358d555204258cd70c6e292..6446e6df7a9ac2fb0272a9a67a6e90fdcd88330e 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi
@@ -141,6 +141,22 @@ lsio_subsys: bus@5d000000 {
                status = "disabled";
        };
 
+       lsio_mu5: mailbox@5d200000 {
+               reg = <0x5d200000 0x10000>;
+               interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+               #mbox-cells = <2>;
+               power-domains = <&pd IMX_SC_R_MU_5A>;
+               status = "disabled";
+       };
+
+       lsio_mu6: mailbox@5d210000 {
+               reg = <0x5d210000 0x10000>;
+               interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
+               #mbox-cells = <2>;
+               power-domains = <&pd IMX_SC_R_MU_6A>;
+               status = "disabled";
+       };
+
        lsio_mu13: mailbox@5d280000 {
                reg = <0x5d280000 0x10000>;
                interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;

diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
index 30896610c6547d47a2db600df226949a060a627c..669aa14ce9f75c2c7eb0e951d688466d26525a77 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lsio.dtsi
@@ -56,6 +56,14 @@
        compatible = "fsl,imx8-mu-scu", "fsl,imx8qm-mu", "fsl,imx6sx-mu";
 };
 
+&lsio_mu5 {
+       compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu6 {
+       compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
+};
+
 &lsio_mu13 {
        compatible = "fsl,imx8qm-mu", "fsl,imx6sx-mu";
 };

diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
index 11395479ffc0125ade09f436cf253a9222bbaa55..8e2152c6eb889fb0fa777504d2ad42f7967a760d 100644 (file)
--- a/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-lsio.dtsi
@@ -56,6 +56,14 @@
        compatible = "fsl,imx8-mu-scu", "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 };
 
+&lsio_mu5 {
+       compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
+&lsio_mu6 {
+       compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
+};
+
 &lsio_mu13 {
        compatible = "fsl,imx8qxp-mu", "fsl,imx6sx-mu";
 };