powerpc/64: only book3s/64 supports CONFIG_PPC_64K_PAGES

CONFIG_PPC_64K_PAGES cannot be selected by nohash/64.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>

diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 2d0be82c30619bd405949b64c2847603caf5a67d..5d8e692d647035646d3455b0c4469b53b7899bbc 100644 (file)
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -375,7 +375,6 @@ config ZONE_DMA
 config PGTABLE_LEVELS
        int
        default 2 if !PPC64
-       default 3 if PPC_64K_PAGES && !PPC_BOOK3S_64
        default 4
 
 source "arch/powerpc/sysdev/Kconfig"

diff --git a/arch/powerpc/include/asm/nohash/64/pgalloc.h b/arch/powerpc/include/asm/nohash/64/pgalloc.h
index 66d086f85bd5b1a9b7f3071b111e3b819dd346ef..ded453f9b5a8aec470bb8a47af4472f46f83b649 100644 (file)
--- a/arch/powerpc/include/asm/nohash/64/pgalloc.h
+++ b/arch/powerpc/include/asm/nohash/64/pgalloc.h
@@ -171,12 +171,9 @@ static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t table,
 
 #define __pmd_free_tlb(tlb, pmd, addr)               \
        pgtable_free_tlb(tlb, pmd, PMD_CACHE_INDEX)
-#ifndef CONFIG_PPC_64K_PAGES
 #define __pud_free_tlb(tlb, pud, addr)               \
        pgtable_free_tlb(tlb, pud, PUD_INDEX_SIZE)
 
-#endif /* CONFIG_PPC_64K_PAGES */
-
 #define check_pgt_cache()      do { } while (0)
 
 #endif /* _ASM_POWERPC_PGALLOC_64_H */

diff --git a/arch/powerpc/include/asm/nohash/64/pgtable.h b/arch/powerpc/include/asm/nohash/64/pgtable.h
index c8e6a9a5bc33f045e88e5c78a5b58bbd28fdfdeb..b9f66cf15c310a0910316b5e386cf79d3f042de4 100644 (file)
--- a/arch/powerpc/include/asm/nohash/64/pgtable.h
+++ b/arch/powerpc/include/asm/nohash/64/pgtable.h
@@ -10,10 +10,6 @@
 #include <asm/barrier.h>
 #include <asm/asm-const.h>
 
-#ifdef CONFIG_PPC_64K_PAGES
-#error "Page size not supported"
-#endif
-
 #define FIRST_USER_ADDRESS     0UL
 
 /*

diff --git a/arch/powerpc/include/asm/nohash/pte-book3e.h b/arch/powerpc/include/asm/nohash/pte-book3e.h
index dd40d200f274267c88080d51512aa773e3bfa96e..813918f4076534b91494ccc5803158ad25d4f99f 100644 (file)
--- a/arch/powerpc/include/asm/nohash/pte-book3e.h
+++ b/arch/powerpc/include/asm/nohash/pte-book3e.h
@@ -60,13 +60,8 @@
 #define _PAGE_SPECIAL  _PAGE_SW0
 
 /* Base page size */
-#ifdef CONFIG_PPC_64K_PAGES
-#define _PAGE_PSIZE    _PAGE_PSIZE_64K
-#define PTE_RPN_SHIFT  (28)
-#else
 #define _PAGE_PSIZE    _PAGE_PSIZE_4K
 #define        PTE_RPN_SHIFT   (24)
-#endif
 
 #define PTE_WIMGE_SHIFT (19)
 #define PTE_BAP_SHIFT  (2)

diff --git a/arch/powerpc/include/asm/pgtable-be-types.h b/arch/powerpc/include/asm/pgtable-be-types.h
index a89c67b626801bd64dcc5ef6fde5ad900f9f7ba2..b169bbf95fcbe2232438442ccd9e827de872ed61 100644 (file)
--- a/arch/powerpc/include/asm/pgtable-be-types.h
+++ b/arch/powerpc/include/asm/pgtable-be-types.h
@@ -33,11 +33,7 @@ static inline __be64 pmd_raw(pmd_t x)
        return x.pmd;
 }
 
-/*
- * 64 bit hash always use 4 level table. Everybody else use 4 level
- * only for 4K page size.
- */
-#if defined(CONFIG_PPC_BOOK3S_64) || !defined(CONFIG_PPC_64K_PAGES)
+/* 64 bit always use 4 level table. */
 typedef struct { __be64 pud; } pud_t;
 #define __pud(x)       ((pud_t) { cpu_to_be64(x) })
 #define __pud_raw(x)   ((pud_t) { (x) })
@@ -51,7 +47,6 @@ static inline __be64 pud_raw(pud_t x)
        return x.pud;
 }
 
-#endif /* CONFIG_PPC_BOOK3S_64 || !CONFIG_PPC_64K_PAGES */
 #endif /* CONFIG_PPC64 */
 
 /* PGD level */
@@ -77,7 +72,7 @@ typedef struct { unsigned long pgprot; } pgprot_t;
  * With hash config 64k pages additionally define a bigger "real PTE" type that
  * gathers the "second half" part of the PTE for pseudo 64k pages
  */
-#if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC_BOOK3S_64)
+#ifdef CONFIG_PPC_64K_PAGES
 typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;
 #else
 typedef struct { pte_t pte; } real_pte_t;

diff --git a/arch/powerpc/include/asm/pgtable-types.h b/arch/powerpc/include/asm/pgtable-types.h
index 3b0edf041b2e16ce7e93a8026432bc269e11d927..d11b4c61d686a2ec63f732af3347836f43328315 100644 (file)
--- a/arch/powerpc/include/asm/pgtable-types.h
+++ b/arch/powerpc/include/asm/pgtable-types.h
@@ -23,18 +23,13 @@ static inline unsigned long pmd_val(pmd_t x)
        return x.pmd;
 }
 
-/*
- * 64 bit hash always use 4 level table. Everybody else use 4 level
- * only for 4K page size.
- */
-#if defined(CONFIG_PPC_BOOK3S_64) || !defined(CONFIG_PPC_64K_PAGES)
+/* 64 bit always use 4 level table. */
 typedef struct { unsigned long pud; } pud_t;
 #define __pud(x)       ((pud_t) { (x) })
 static inline unsigned long pud_val(pud_t x)
 {
        return x.pud;
 }
-#endif /* CONFIG_PPC_BOOK3S_64 || !CONFIG_PPC_64K_PAGES */
 #endif /* CONFIG_PPC64 */
 
 /* PGD level */
@@ -54,7 +49,7 @@ typedef struct { unsigned long pgprot; } pgprot_t;
  * With hash config 64k pages additionally define a bigger "real PTE" type that
  * gathers the "second half" part of the PTE for pseudo 64k pages
  */
-#if defined(CONFIG_PPC_64K_PAGES) && defined(CONFIG_PPC_BOOK3S_64)
+#ifdef CONFIG_PPC_64K_PAGES
 typedef struct { pte_t pte; unsigned long hidx; } real_pte_t;
 #else
 typedef struct { pte_t pte; } real_pte_t;

diff --git a/arch/powerpc/include/asm/task_size_64.h b/arch/powerpc/include/asm/task_size_64.h
index eab4779f6b84974f5ee97ebcda2e26f97db51e26..c993482237edc4367ef415951aa6e1cce588492c 100644 (file)
--- a/arch/powerpc/include/asm/task_size_64.h
+++ b/arch/powerpc/include/asm/task_size_64.h
@@ -20,7 +20,7 @@
 /*
  * For now 512TB is only supported with book3s and 64K linux page size.
  */
-#if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_PPC_64K_PAGES)
+#ifdef CONFIG_PPC_64K_PAGES
 /*
  * Max value currently used:
  */

diff --git a/arch/powerpc/mm/nohash/tlb.c b/arch/powerpc/mm/nohash/tlb.c
index c2494b8380089c0ea66f81344deed44abdca0068..24f88efb05bf244546eb297ff3bd1f125b57baae 100644 (file)
--- a/arch/powerpc/mm/nohash/tlb.c
+++ b/arch/powerpc/mm/nohash/tlb.c
@@ -433,11 +433,7 @@ void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
                unsigned long rid = (address & rmask) | 0x1000000000000000ul;
                unsigned long vpte = address & ~rmask;
 
-#ifdef CONFIG_PPC_64K_PAGES
-               vpte = (vpte >> (PAGE_SHIFT - 4)) & ~0xfffful;
-#else
                vpte = (vpte >> (PAGE_SHIFT - 3)) & ~0xffful;
-#endif
                vpte |= rid;
                __flush_tlb_page(tlb->mm, vpte, tsize, 0);
        }
@@ -625,21 +621,12 @@ static void early_init_this_mmu(void)
 
        case PPC_HTW_IBM:
                mas4 |= MAS4_INDD;
-#ifdef CONFIG_PPC_64K_PAGES
-               mas4 |= BOOK3E_PAGESZ_256M << MAS4_TSIZED_SHIFT;
-               mmu_pte_psize = MMU_PAGE_256M;
-#else
                mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT;
                mmu_pte_psize = MMU_PAGE_1M;
-#endif
                break;
 
        case PPC_HTW_NONE:
-#ifdef CONFIG_PPC_64K_PAGES
-               mas4 |= BOOK3E_PAGESZ_64K << MAS4_TSIZED_SHIFT;
-#else
                mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
-#endif
                mmu_pte_psize = mmu_virtual_psize;
                break;
        }

diff --git a/arch/powerpc/mm/nohash/tlb_low_64e.S b/arch/powerpc/mm/nohash/tlb_low_64e.S
index 9ed90064f54292ea5774841b4d13b9276dc171ac..58959ce15415c0e605988d2e9ca4419e626d295e 100644 (file)
--- a/arch/powerpc/mm/nohash/tlb_low_64e.S
+++ b/arch/powerpc/mm/nohash/tlb_low_64e.S
@@ -24,11 +24,7 @@
 #include <asm/kvm_booke_hv_asm.h>
 #include <asm/feature-fixups.h>
 
-#ifdef CONFIG_PPC_64K_PAGES
-#define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1)
-#else
 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE)
-#endif
 #define VPTE_PUD_SHIFT (VPTE_PMD_SHIFT + PMD_INDEX_SIZE)
 #define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE)
 #define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE)
@@ -167,13 +163,11 @@ MMU_FTR_SECTION_ELSE
        ldx     r14,r14,r15             /* grab pgd entry */
 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
 
-#ifndef CONFIG_PPC_64K_PAGES
        rldicl  r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
        clrrdi  r15,r15,3
        cmpdi   cr0,r14,0
        bge     tlb_miss_fault_bolted   /* Bad pgd entry or hugepage; bail */
        ldx     r14,r14,r15             /* grab pud entry */
-#endif /* CONFIG_PPC_64K_PAGES */
 
        rldicl  r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
        clrrdi  r15,r15,3
@@ -682,18 +676,7 @@ normal_tlb_miss:
         * order to handle the weird page table format used by linux
         */
        ori     r10,r15,0x1
-#ifdef CONFIG_PPC_64K_PAGES
-       /* For the top bits, 16 bytes per PTE */
-       rldicl  r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4
-       /* Now create the bottom bits as 0 in position 0x8000 and
-        * the rest calculated for 8 bytes per PTE
-        */
-       rldicl  r15,r16,64-(PAGE_SHIFT-3),64-15
-       /* Insert the bottom bits in */
-       rlwimi  r14,r15,0,16,31
-#else
        rldicl  r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4
-#endif
        sldi    r15,r10,60
        clrrdi  r14,r14,3
        or      r10,r15,r14
@@ -732,11 +715,7 @@ finish_normal_tlb_miss:
 
        /* Check page size, if not standard, update MAS1 */
        rldicl  r11,r14,64-8,64-8
-#ifdef CONFIG_PPC_64K_PAGES
-       cmpldi  cr0,r11,BOOK3E_PAGESZ_64K
-#else
        cmpldi  cr0,r11,BOOK3E_PAGESZ_4K
-#endif
        beq-    1f
        mfspr   r11,SPRN_MAS1
        rlwimi  r11,r14,31,21,24
@@ -857,14 +836,12 @@ END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
        cmpdi   cr0,r15,0
        bge     virt_page_table_tlb_miss_fault
 
-#ifndef CONFIG_PPC_64K_PAGES
        /* Get to PUD entry */
        rldicl  r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3
        clrrdi  r10,r11,3
        ldx     r15,r10,r15
        cmpdi   cr0,r15,0
        bge     virt_page_table_tlb_miss_fault
-#endif /* CONFIG_PPC_64K_PAGES */
 
        /* Get to PMD entry */
        rldicl  r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3
@@ -1106,14 +1083,12 @@ htw_tlb_miss:
        cmpdi   cr0,r15,0
        bge     htw_tlb_miss_fault
 
-#ifndef CONFIG_PPC_64K_PAGES
        /* Get to PUD entry */
        rldicl  r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3
        clrrdi  r10,r11,3
        ldx     r15,r10,r15
        cmpdi   cr0,r15,0
        bge     htw_tlb_miss_fault
-#endif /* CONFIG_PPC_64K_PAGES */
 
        /* Get to PMD entry */
        rldicl  r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3
@@ -1132,9 +1107,7 @@ htw_tlb_miss:
         * 4K page we need to extract a bit from the virtual address and
         * insert it into the "PA52" bit of the RPN.
         */
-#ifndef CONFIG_PPC_64K_PAGES
        rlwimi  r15,r16,32-9,20,20
-#endif
        /* Now we build the MAS:
         *
         * MAS 0   :    Fully setup with defaults in MAS4 and TLBnCFG
@@ -1144,11 +1117,7 @@ htw_tlb_miss:
         * MAS 2   :    Use defaults
         * MAS 3+7 :    Needs to be done
         */
-#ifdef CONFIG_PPC_64K_PAGES
-       ori     r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT)
-#else
        ori     r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
-#endif
 
 BEGIN_MMU_FTR_SECTION
        srdi    r16,r10,32