#define DESC_FLAG_NWD BIT(12)
#define DESC_FLAG_CMD BIT(11)
+#define BAM_NDP_REVISION_START 0x20
+#define BAM_NDP_REVISION_END 0x27
+
struct bam_async_desc {
struct virt_dma_desc vd;
/* dma start transaction tasklet */
struct tasklet_struct task;
+ u32 bam_revision;
};
/**
writel_relaxed(val, bam_addr(bdev, 0, BAM_CTRL));
/* set descriptor threshold, start with 4 bytes */
- writel_relaxed(DEFAULT_CNT_THRSHLD,
- bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
+ if (in_range(bdev->bam_revision, BAM_NDP_REVISION_START,
+ BAM_NDP_REVISION_END))
+ writel_relaxed(DEFAULT_CNT_THRSHLD,
+ bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
/* Enable default set of h/w workarounds, ie all except BAM_FULL_PIPE */
writel_relaxed(BAM_CNFG_BITS_DEFAULT, bam_addr(bdev, 0, BAM_CNFG_BITS));
maxburst = bchan->slave.src_maxburst;
else
maxburst = bchan->slave.dst_maxburst;
-
- writel_relaxed(maxburst,
- bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
+ if (in_range(bdev->bam_revision, BAM_NDP_REVISION_START,
+ BAM_NDP_REVISION_END))
+ writel_relaxed(maxburst,
+ bam_addr(bdev, 0, BAM_DESC_CNT_TRSHLD));
}
bchan->reconfigure = 0;
u32 val;
/* read revision and configuration information */
- if (!bdev->num_ees) {
- val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION));
+ val = readl_relaxed(bam_addr(bdev, 0, BAM_REVISION));
+ if (!bdev->num_ees)
bdev->num_ees = (val >> NUM_EES_SHIFT) & NUM_EES_MASK;
- }
+
+ bdev->bam_revision = val & REVISION_MASK;
/* check that configured EE is within range */
if (bdev->ee >= bdev->num_ees)