arm64: tegra: Enable DFLL support on Jetson Nano

Populate the DFLL node and corresponding PWM pin nodes in order to
enable CPUFREQ support on the Jetson Nano platform.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
index 9b6346917ea9d4d2ab98f893aadc775edebf84eb..2282ea1c62793cd6c510d16900501db9eb892d80 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
+++ b/arch/arm64/boot/dts/nvidia/tegra210-p3450-0000.dts
@@ -111,6 +111,22 @@
                status = "okay";
        };
 
+       pinmux@700008d4 {
+               dvfs_pwm_active_state: dvfs_pwm_active {
+                       dvfs_pwm_pbb1 {
+                               nvidia,pins = "dvfs_pwm_pbb1";
+                               nvidia,tristate = <TEGRA_PIN_DISABLE>;
+                       };
+               };
+
+               dvfs_pwm_inactive_state: dvfs_pwm_inactive {
+                       dvfs_pwm_pbb1 {
+                               nvidia,pins = "dvfs_pwm_pbb1";
+                               nvidia,tristate = <TEGRA_PIN_ENABLE>;
+                       };
+               };
+       };
+
        /* debug port */
        serial@70006000 {
                status = "okay";
@@ -584,6 +600,27 @@
                hvdd-usb-supply = <&vdd_1v8>;
        };
 
+       clock@70110000 {
+               status = "okay";
+
+               nvidia,cf = <6>;
+               nvidia,ci = <0>;
+               nvidia,cg = <2>;
+               nvidia,droop-ctrl = <0x00000f00>;
+               nvidia,force-mode = <1>;
+               nvidia,sample-rate = <25000>;
+
+               nvidia,pwm-min-microvolts = <708000>;
+               nvidia,pwm-period-nanoseconds = <2500>; /* 2.5us */
+               nvidia,pwm-to-pmic;
+               nvidia,pwm-tristate-microvolts = <1000000>;
+               nvidia,pwm-voltage-step-microvolts = <19200>;
+
+               pinctrl-names = "dvfs_pwm_enable", "dvfs_pwm_disable";
+               pinctrl-0 = <&dvfs_pwm_active_state>;
+               pinctrl-1 = <&dvfs_pwm_inactive_state>;
+       };
+
        clk32k_in: clock@0 {
                compatible = "fixed-clock";
                clock-frequency = <32768>;