The doorbell register on GB20x GPUs has additional fields.
Signed-off-by: Ben Skeggs <bskeggs@nvidia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timur Tabi <ttabi@nvidia.com>
Tested-by: Timur Tabi <ttabi@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
#include <core/enum.h>
struct nvkm_cctx;
struct nvkm_cgrp;
+struct nvkm_chan;
struct nvkm_engn;
struct nvkm_memory;
struct nvkm_runl;
void tu102_fifo_intr_ctxsw_timeout_info(struct nvkm_engn *, u32 info);
extern const struct nvkm_fifo_func_mmu_fault tu102_fifo_mmu_fault;
+u32 tu102_chan_doorbell_handle(struct nvkm_chan *);
int ga100_fifo_runl_ctor(struct nvkm_fifo *);
int ga100_fifo_nonstall_ctor(struct nvkm_fifo *);
#include <nvif/class.h>
-static u32
+u32
tu102_chan_doorbell_handle(struct nvkm_chan *chan)
{
return (chan->cgrp->runl->id << 16) | chan->id;
*/
#include "gpu.h"
+#include <engine/fifo/priv.h>
+
#include <nvif/class.h>
const struct nvkm_rm_gpu
.fifo.chan = {
.class = AMPERE_CHANNEL_GPFIFO_A,
+ .doorbell_handle = tu102_chan_doorbell_handle,
},
.ce.class = AMPERE_DMA_COPY_B,
*/
#include "gpu.h"
+#include <engine/fifo/priv.h>
+
#include <nvif/class.h>
const struct nvkm_rm_gpu
.fifo.chan = {
.class = AMPERE_CHANNEL_GPFIFO_A,
+ .doorbell_handle = tu102_chan_doorbell_handle,
},
.ce.class = AMPERE_DMA_COPY_A,
*/
#include "gpu.h"
+#include <engine/fifo/priv.h>
+
#include <nvif/class.h>
const struct nvkm_rm_gpu
.fifo.chan = {
.class = AMPERE_CHANNEL_GPFIFO_A,
+ .doorbell_handle = tu102_chan_doorbell_handle,
},
.ce.class = AMPERE_DMA_COPY_B,
*/
#include "gpu.h"
+#include <engine/fifo/priv.h>
+
#include <nvif/class.h>
const struct nvkm_rm_gpu
.fifo.chan = {
.class = BLACKWELL_CHANNEL_GPFIFO_A,
+ .doorbell_handle = tu102_chan_doorbell_handle,
},
.ce.class = BLACKWELL_DMA_COPY_A,
*/
#include "gpu.h"
+#include <engine/fifo/priv.h>
+
#include <nvif/class.h>
const struct nvkm_rm_gpu
.fifo.chan = {
.class = HOPPER_CHANNEL_GPFIFO_A,
+ .doorbell_handle = tu102_chan_doorbell_handle,
},
.ce.class = HOPPER_DMA_COPY_A,
struct {
struct {
u32 class;
+ u32 (*doorbell_handle)(struct nvkm_chan *);
} chan;
} fifo;
static u32
r535_chan_doorbell_handle(struct nvkm_chan *chan)
{
- return (chan->cgrp->runl->id << 16) | chan->id;
+ struct nvkm_gsp *gsp = chan->rm.object.client->gsp;
+
+ return gsp->rm->gpu->fifo.chan.doorbell_handle(chan);
}
static void
*/
#include "gpu.h"
+#include <engine/fifo/priv.h>
+
#include <nvif/class.h>
const struct nvkm_rm_gpu
.fifo.chan = {
.class = TURING_CHANNEL_GPFIFO_A,
+ .doorbell_handle = tu102_chan_doorbell_handle,
},
.ce.class = TURING_DMA_COPY_A,