drm/nouveau/gsp: add hal for fifo.chan.doorbell_handle
authorBen Skeggs <bskeggs@nvidia.com>
Tue, 25 Feb 2025 21:49:00 +0000 (07:49 +1000)
committerDave Airlie <airlied@redhat.com>
Sun, 18 May 2025 21:14:44 +0000 (07:14 +1000)
The doorbell register on GB20x GPUs has additional fields.

Signed-off-by: Ben Skeggs <bskeggs@nvidia.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Timur Tabi <ttabi@nvidia.com>
Tested-by: Timur Tabi <ttabi@nvidia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/nouveau/nvkm/engine/fifo/priv.h
drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.c
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ad10x.c
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ga100.c
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/ga1xx.c
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gb10x.c
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gh100.c
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/gpu.h
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/r535/fifo.c
drivers/gpu/drm/nouveau/nvkm/subdev/gsp/rm/tu1xx.c

index a0f3277605a5cf4e21d6501e23c07b4704c4be07..9ebb35c31db0c048df1be2ec94cee2bf0fec00e9 100644 (file)
@@ -6,6 +6,7 @@
 #include <core/enum.h>
 struct nvkm_cctx;
 struct nvkm_cgrp;
+struct nvkm_chan;
 struct nvkm_engn;
 struct nvkm_memory;
 struct nvkm_runl;
@@ -195,6 +196,7 @@ extern const struct nvkm_chan_func_ramfc gv100_chan_ramfc;
 
 void tu102_fifo_intr_ctxsw_timeout_info(struct nvkm_engn *, u32 info);
 extern const struct nvkm_fifo_func_mmu_fault tu102_fifo_mmu_fault;
+u32 tu102_chan_doorbell_handle(struct nvkm_chan *);
 
 int ga100_fifo_runl_ctor(struct nvkm_fifo *);
 int ga100_fifo_nonstall_ctor(struct nvkm_fifo *);
index 1d39a6840a404d1409758db65d935b1c3a1cad72..c5a03298e88c1fded07d325d837561fb744f73a8 100644 (file)
@@ -31,7 +31,7 @@
 
 #include <nvif/class.h>
 
-static u32
+u32
 tu102_chan_doorbell_handle(struct nvkm_chan *chan)
 {
        return (chan->cgrp->runl->id << 16) | chan->id;
index d699c386adec62335eb8700ec5ece4a20281d206..e1ce6355c35f7397c2e5cddbd3c8e0022beed9a0 100644 (file)
@@ -4,6 +4,8 @@
  */
 #include "gpu.h"
 
+#include <engine/fifo/priv.h>
+
 #include <nvif/class.h>
 
 const struct nvkm_rm_gpu
@@ -21,6 +23,7 @@ ad10x_gpu = {
 
        .fifo.chan = {
                .class = AMPERE_CHANNEL_GPFIFO_A,
+               .doorbell_handle = tu102_chan_doorbell_handle,
        },
 
        .ce.class = AMPERE_DMA_COPY_B,
index 5e7f18dbf18b30e4b0e8a3b6225d1e18974da485..a48c6134075d3949b46e57a70acdb09576458300 100644 (file)
@@ -4,6 +4,8 @@
  */
 #include "gpu.h"
 
+#include <engine/fifo/priv.h>
+
 #include <nvif/class.h>
 
 const struct nvkm_rm_gpu
@@ -12,6 +14,7 @@ ga100_gpu = {
 
        .fifo.chan = {
                .class = AMPERE_CHANNEL_GPFIFO_A,
+               .doorbell_handle = tu102_chan_doorbell_handle,
        },
 
        .ce.class = AMPERE_DMA_COPY_A,
index 61525d23aaa04bc815046d9e2dfec2f2610dcbad..50536ad7f85d72ffc94c403fc3ddc898f23bf168 100644 (file)
@@ -4,6 +4,8 @@
  */
 #include "gpu.h"
 
+#include <engine/fifo/priv.h>
+
 #include <nvif/class.h>
 
 const struct nvkm_rm_gpu
@@ -21,6 +23,7 @@ ga1xx_gpu = {
 
        .fifo.chan = {
                .class = AMPERE_CHANNEL_GPFIFO_A,
+               .doorbell_handle = tu102_chan_doorbell_handle,
        },
 
        .ce.class = AMPERE_DMA_COPY_B,
index 3a296d8fd2e099fa2b59e90df21a026214ecd0d8..2f517dcd721a64570e81b4f33b6bf7b6d9a4fe00 100644 (file)
@@ -4,6 +4,8 @@
  */
 #include "gpu.h"
 
+#include <engine/fifo/priv.h>
+
 #include <nvif/class.h>
 
 const struct nvkm_rm_gpu
@@ -12,6 +14,7 @@ gb10x_gpu = {
 
        .fifo.chan = {
                .class = BLACKWELL_CHANNEL_GPFIFO_A,
+               .doorbell_handle = tu102_chan_doorbell_handle,
        },
 
        .ce.class = BLACKWELL_DMA_COPY_A,
index 088250559e122cf386cb115f040e430dd5f85e7d..49e2c54e1aa8e9bcfd3dfcfc111a7017b822f5dd 100644 (file)
@@ -4,6 +4,8 @@
  */
 #include "gpu.h"
 
+#include <engine/fifo/priv.h>
+
 #include <nvif/class.h>
 
 const struct nvkm_rm_gpu
@@ -12,6 +14,7 @@ gh100_gpu = {
 
        .fifo.chan = {
                .class = HOPPER_CHANNEL_GPFIFO_A,
+               .doorbell_handle = tu102_chan_doorbell_handle,
        },
 
        .ce.class = HOPPER_DMA_COPY_A,
index e84376c85e99ebe0bc4a5540ed6cbbb0c0ded42a..77aa7b13a3afc006cb1ee717b0ee41c3645a1007 100644 (file)
@@ -25,6 +25,7 @@ struct nvkm_rm_gpu {
        struct {
                struct {
                        u32 class;
+                       u32 (*doorbell_handle)(struct nvkm_chan *);
                } chan;
        } fifo;
 
index 4238362ec073e9a6d468fb1ebea1720d77878f20..eaba4d50860d7e3410fd3fa7d55ba6b5c571a626 100644 (file)
@@ -41,7 +41,9 @@
 static u32
 r535_chan_doorbell_handle(struct nvkm_chan *chan)
 {
-       return (chan->cgrp->runl->id << 16) | chan->id;
+       struct nvkm_gsp *gsp = chan->rm.object.client->gsp;
+
+       return gsp->rm->gpu->fifo.chan.doorbell_handle(chan);
 }
 
 static void
index 883b9eddbfe62a2fe843d60cea9da1721246616e..423502f870db758dba7052d47a5a34b4b4350c89 100644 (file)
@@ -4,6 +4,8 @@
  */
 #include "gpu.h"
 
+#include <engine/fifo/priv.h>
+
 #include <nvif/class.h>
 
 const struct nvkm_rm_gpu
@@ -21,6 +23,7 @@ tu1xx_gpu = {
 
        .fifo.chan = {
                .class = TURING_CHANNEL_GPFIFO_A,
+               .doorbell_handle = tu102_chan_doorbell_handle,
        },
 
        .ce.class = TURING_DMA_COPY_A,