drm/amdgpu: Fix undue fallthroughs in golden registers initialization
authorJean Delvare <jdelvare@suse.de>
Sun, 30 Jul 2017 08:18:25 +0000 (10:18 +0200)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 2 Aug 2017 18:29:42 +0000 (14:29 -0400)
As I was staring at the si_init_golden_registers code, I noticed that
the Pitcairn initialization silently falls through the Cape Verde
initialization, and the Oland initialization falls through the Hainan
initialization. However there is no comment stating that this is
intentional, and the radeon driver doesn't have any such fallthrough,
so I suspect this is not supposed to happen.

Signed-off-by: Jean Delvare <jdelvare@suse.de>
Fixes: 62a37553414a ("drm/amdgpu: add si implementation v10")
Cc: Ken Wang <Qingqing.Wang@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: "Marek Olšák" <maraeo@gmail.com>
Cc: "Christian König" <christian.koenig@amd.com>
Cc: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
drivers/gpu/drm/amd/amdgpu/si.c

index f45fb0f022b3c6480b08afa545f4e3f4f9381610..4267fa417997aeaf6336297f25a05c31c7ae4eb8 100644 (file)
@@ -1385,6 +1385,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
                amdgpu_program_register_sequence(adev,
                                                 pitcairn_mgcg_cgcg_init,
                                                 (const u32)ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
+               break;
        case CHIP_VERDE:
                amdgpu_program_register_sequence(adev,
                                                 verde_golden_registers,
@@ -1409,6 +1410,7 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
                amdgpu_program_register_sequence(adev,
                                                 oland_mgcg_cgcg_init,
                                                 (const u32)ARRAY_SIZE(oland_mgcg_cgcg_init));
+               break;
        case CHIP_HAINAN:
                amdgpu_program_register_sequence(adev,
                                                 hainan_golden_registers,