net: hns3: cleanup for endian issue for VF RSS

Currently the RSS commands of VF are using host byte order.
According to the user manual, it should use little endian in
the command to firmware. For the host and firmware are both
using little endian, so it can work well in this case.

Do cleanup to make it more explicitly.

Signed-off-by: Jian Shen <shenjian15@huawei.com>
Signed-off-by: Huazhong tan <tanhuazhong@huawei.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
index 2a6aaffb9e9a7163b74ad707c7f5bcd8b1d52ed0..8a37a22a176b2c99b5907209d35493809f5c5e01 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.h
@@ -216,8 +216,8 @@ struct hclgevf_rss_input_tuple_cmd {
 #define HCLGEVF_RSS_CFG_TBL_SIZE       16
 
 struct hclgevf_rss_indirection_table_cmd {
-       u16 start_table_index;
-       u16 rss_set_bitmap;
+       __le16 start_table_index;
+       __le16 rss_set_bitmap;
        u8 rsv[4];
        u8 rss_result[HCLGEVF_RSS_CFG_TBL_SIZE];
 };
@@ -229,7 +229,7 @@ struct hclgevf_rss_indirection_table_cmd {
 #define HCLGEVF_RSS_TC_VALID_B         15
 #define HCLGEVF_MAX_TC_NUM             8
 struct hclgevf_rss_tc_mode_cmd {
-       u16 rss_tc_mode[HCLGEVF_MAX_TC_NUM];
+       __le16 rss_tc_mode[HCLGEVF_MAX_TC_NUM];
        u8 rsv[8];
 };
 

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
index ab213ad2f83052b23bdbc69b1254e08656e4882f..ece31693e6247db056be1f2a429418b808cebf1b 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
@@ -658,8 +658,9 @@ static int hclgevf_set_rss_indir_table(struct hclgevf_dev *hdev)
        for (i = 0; i < rss_cfg_tbl_num; i++) {
                hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_INDIR_TABLE,
                                             false);
-               req->start_table_index = i * HCLGEVF_RSS_CFG_TBL_SIZE;
-               req->rss_set_bitmap = HCLGEVF_RSS_SET_BITMAP_MSK;
+               req->start_table_index =
+                       cpu_to_le16(i * HCLGEVF_RSS_CFG_TBL_SIZE);
+               req->rss_set_bitmap = cpu_to_le16(HCLGEVF_RSS_SET_BITMAP_MSK);
                for (j = 0; j < HCLGEVF_RSS_CFG_TBL_SIZE; j++)
                        req->rss_result[j] =
                                indir[i * HCLGEVF_RSS_CFG_TBL_SIZE + j];
@@ -700,12 +701,16 @@ static int hclgevf_set_rss_tc_mode(struct hclgevf_dev *hdev,  u16 rss_size)
 
        hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_RSS_TC_MODE, false);
        for (i = 0; i < HCLGEVF_MAX_TC_NUM; i++) {
-               hnae3_set_bit(req->rss_tc_mode[i], HCLGEVF_RSS_TC_VALID_B,
+               u16 mode = 0;
+
+               hnae3_set_bit(mode, HCLGEVF_RSS_TC_VALID_B,
                              (tc_valid[i] & 0x1));
-               hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_SIZE_M,
+               hnae3_set_field(mode, HCLGEVF_RSS_TC_SIZE_M,
                                HCLGEVF_RSS_TC_SIZE_S, tc_size[i]);
-               hnae3_set_field(req->rss_tc_mode[i], HCLGEVF_RSS_TC_OFFSET_M,
+               hnae3_set_field(mode, HCLGEVF_RSS_TC_OFFSET_M,
                                HCLGEVF_RSS_TC_OFFSET_S, tc_offset[i]);
+
+               req->rss_tc_mode[i] = cpu_to_le16(mode);
        }
        status = hclgevf_cmd_send(&hdev->hw, &desc, 1);
        if (status)